CFP last date
20 May 2024
Reseach Article

Design of RS and D-Flip-Flop using AlGaAs/GaAs MODFET Technology

by Ganesan. V, Shaji. K. S
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 83 - Number 8
Year of Publication: 2013
Authors: Ganesan. V, Shaji. K. S
10.5120/14468-2751

Ganesan. V, Shaji. K. S . Design of RS and D-Flip-Flop using AlGaAs/GaAs MODFET Technology. International Journal of Computer Applications. 83, 8 ( December 2013), 16-20. DOI=10.5120/14468-2751

@article{ 10.5120/14468-2751,
author = { Ganesan. V, Shaji. K. S },
title = { Design of RS and D-Flip-Flop using AlGaAs/GaAs MODFET Technology },
journal = { International Journal of Computer Applications },
issue_date = { December 2013 },
volume = { 83 },
number = { 8 },
month = { December },
year = { 2013 },
issn = { 0975-8887 },
pages = { 16-20 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume83/number8/14468-2751/ },
doi = { 10.5120/14468-2751 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:58:48.759836+05:30
%A Ganesan. V
%A Shaji. K. S
%T Design of RS and D-Flip-Flop using AlGaAs/GaAs MODFET Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 83
%N 8
%P 16-20
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper enumerates high speed design of RS & D- flip-flop using AlGaAs/GaAs MODFET. The proposed Flip Flop is having less number of transistors than existing designs. Simulation results show lowest average power and least delay than existing designs. This Flip-Flop having less number of transistors. It can be efficiently used in VLSI ICs. In the verification by simulation, the proposed flip-flops appear to have better speed of operation. It is simple and suitable to SPICE simulation of hybrid digital ICs.

References
  1. Imran Ahmed Khan, Danish Shaikh and Mirza Tariq Beg,, "2 GHz Low Power Double Edge Triggered flip- flop in 65nm CMOS Technology," IEEE Conference, 2012.
  2. Xiaowen Wang and William H. Robinson, "A Low-Power Double Edge-Triggered Flip-Flop with Transmission Gates and Clock Gating," IEEE Conference, pp 205-208, 2010.
  3. Yu Chien-Cheng,, "Low-Power Double Edge- Triggered Flip-Flop Circuit Design," Third International Conference on Innovative Computing Information and Control (ICICIC'08), IEEE Conference, 2008. [4 Kandukuru (M); Prakasam(Dt), "Design Approaches for Low power-Low area D flip flop in Nano Technology," International Journal of Electronics Signals and Systems (IJESS) ISSN: 2231- 5969, Vol-2 Iss-1, 2012
  4. Peiyi Zhao, Jason McNeely, Pradeep Golconda and Jianping Hu, "Low Power Design of Double-Edge Triggered Flip-Flop by Reducing the Number of Clocked Transistors," IEEE Conference, 2008.
  5. Sandeep Sriram, Arun Ramnath, Haiqing, Hojoon Lee and Ken Choi "A Novel Dual Edge Triggered Near-Threshold State Retentive Latch Design," IEEE Conference, 2011.
  6. Peiyi Zhao, Jason McNeely, Pradeep Golconda and Jianping Hu, "Low Power Design of Double-Edge Triggered Flip-Flop by Reducing the Number of Clocked Transistors," IEEE Conference, 2008.
  7. M. Pedram, Q. Wu, and X. Wu, "A New Design of Double Edge Triggered Flip-Flops," Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 417–421, 1998.
  8. Troy A. JohnsonP and Ivan S. Kourtev , "A Single Latch, High Speed Double-Edge-triggered flip-flop (DETFF)" IEEE, 2001, in press.
  9. Yu Chien-Cheng, "Design of Low-Power Double Edge-Triggered Flip-Flop Circuit", Second IEEE Conference on Industrial Electronics and Applications, pp 2054-2057, 2007.
  10. S. H. Rasouli, A. Amirabadi, A. Seyedi and A. Afazali-kusha, "Double Edge Triggered Feedback Flip-Flop in Sub 100nm Technology," IEEE Conference, 2006.
  11. Wing-Shan Tam, Sik-Lam Siu, Chi-Wah Kok, and Hei Wong. "Double Edge-Triggered Half-Static Clock-Gated D-Type Flip-Flop". IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC), 2010.
  12. Keisuke Inoue and Mineo Kaneko," Variable-Duty -Cycle Scheduling in Double-Edge-Triggered Flip-Flop-Based High-Level Synthesis," IEEE Conference, 2011.
  13. Fatemeh Aezinia, Sara Najafzadeh, and Ali Afzali-Kusha, "Novel High Speed and Low Power Single and Double Edge-Triggered Flip-Flops," IEEE Conference 2006.
  14. Hossein Karimiyan Alidash, Sayed Masoud Sayedi and Hossein Saidi, "Low-Power State-Retention Dual Edge-Triggered Pulsed Latch," Proceedings of ICEE 2010, May 11-13, IEEE 2010.
  15. M. Pedram, "Power minimization in IC Design: Principles and applications," ACM Transactions on Design Automation of Electronic Systems, vol. 1, pp. 3-56, Jan. 1996.
  16. G. E. Tellez, A. Farrahi, and M. Sarafzadeh, "Activity-Driven Clock Design for Low Power Circuits," Proceedings of the IEEWACM International Conference on Computer-Aided Design (ICCAD), pp. 62-65, 1995.
Index Terms

Computer Science
Information Sciences

Keywords

Flip-Flop MODFET delay PDP power consumption.