CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

Performance Analysis of Gate-All-Around Field Effect Transistor for CMOS Nanoscale Devices

by Awanit Sharma, Shyam Akashe
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 84 - Number 10
Year of Publication: 2013
Authors: Awanit Sharma, Shyam Akashe
10.5120/14616-2874

Awanit Sharma, Shyam Akashe . Performance Analysis of Gate-All-Around Field Effect Transistor for CMOS Nanoscale Devices. International Journal of Computer Applications. 84, 10 ( December 2013), 44-48. DOI=10.5120/14616-2874

@article{ 10.5120/14616-2874,
author = { Awanit Sharma, Shyam Akashe },
title = { Performance Analysis of Gate-All-Around Field Effect Transistor for CMOS Nanoscale Devices },
journal = { International Journal of Computer Applications },
issue_date = { December 2013 },
volume = { 84 },
number = { 10 },
month = { December },
year = { 2013 },
issn = { 0975-8887 },
pages = { 44-48 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume84/number10/14616-2874/ },
doi = { 10.5120/14616-2874 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:00:36.267583+05:30
%A Awanit Sharma
%A Shyam Akashe
%T Performance Analysis of Gate-All-Around Field Effect Transistor for CMOS Nanoscale Devices
%J International Journal of Computer Applications
%@ 0975-8887
%V 84
%N 10
%P 44-48
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper explains the performance analysis of Gate-All-Around silicon nanowire with 80nm diameter field effect transistor based CMOS based device utilizing the 45-nm technology. Simulation and analysis of nanowire (NW) CMOS inverter show that there is the reduction of 70% in leakage power and delay minimization of 25% as compared with 180 nm channel length. Gate-All-Aorund (GAA) configuration provides better and low drain induced barrier lowering (DIBL) ~63. 3mV/V and competent Subthresold slope ~95mV/V. GAA achieved the better voltage gain of ~10. 1 V/V . Static noise margin improved with 400mv. It provides high on drive current ~6mA this is validated that the threshold voltage of GAA field effect transistor.

References
  1. Sarunya Bangsaruntip, Guy M. Cohen, Amlan Majumdar, and Jeffrey W. Sleight,"Universality of Short-Channel Effects in Undoped-Body Silicon Nanowire MOSFETs," IEEE Electron Device Lett. , vol. 31, no. 9, pp. 903-905 September 2010
  2. B. Yu, Y. Yuan, J. Song, and Y. Taur," A two dimensional analytical solution for short-channel effects in nanowire MOSFETs,"IEEE Trans. Electron Devices,vol. 56, no. 10, pp. 2357–2362, Oct. 2009
  3. N. Singh, K. D. Buddharaju, S. K. Manhas, A. Agarwal, S. C. Ru ,G. Q. Lo, N. Balasubramanian, and D. L. Kwong, " Si, SiGe nanowire devices by top-down technology and their applications,"IEEE Trans. Electron Devices, vol. 55, no. 11 pp. 3107–3118, Nov. 2008.
  5. N. Singh, A. Agarwal, L. K. Bera, T. Y. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar,G. Q. Lo, N. Balasubramanian, and D. L. Kwong,"High-Performance Fully Depleted Silicon Nanowire (Diameter ? 5 nm) Gate-All-Around CMOS Devices,"IEEE Electron Device Lett. vol. 27, no. 5, pp. 383-386 may 2006.
  6. J. Guo, J. Wang, E. Polizzi, S. Datta, and M. Lundstrom,"Electrostatics of nanowire transistors," IEEE Trans. Nanotechnol. , vol. 2, no. 4 pp. 329–334,Dec. 2003.
  7. S. H. Oh, D. Monroe, and J. M. Hergenrother, "Analytical description of short-channel effects in fully depleted double-gate and cylindrical surrounding-gate MOSFETs," IEEE Electron Device Lett. , vol. 21, no. 9, pp. 445–447, Sep. 2000.
  8. B. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, "High performance fully-depleted tri-gate CMOS transistor," IEEE Electron Device Lett. , vol. 24, no. 4, pp. 263–265, Apr. 2003.
  9. C. P. Auth and J. D. Plummer,"Scaling theory for cylindrical, fullydepleted, surrounding-gate MOSFETs," IEEE Electron Device Lett. , vol. 18, no. 2, pp. 74–76, Feb. 1997
  10. S. H. Oh, D. Monroe, and J. M. Hergenrother, "Analytic description of short-channel effects in fully-depleted double-gate and cylindrical,surrounding-gate MOSFETs,"IEEE ElectronDevice Lett. , vol. 21, no. 9, pp. 445–447, Sep. 2000
  11. B. Yang, K. D. Buddharaju, S. H. G. Teo, N. Singh, G. Q. Lo, and D. L. Kwong," silicon nanowire formation and gate-all-around MOSFET,"IEEE Electron Device Lett. , vol. 29, no. 7, pp. 791–794, July. 2008.
  12. Satish Maheshwaram, S. K. Manhas, Gaurav Kaushal, Bulusu Anand, and Navab singh," silicon nano-wire gate-all-around field effect transistor based nanoscale CMOS," IEEE Electron Device Lett. , vol 32, no. 8, pp. 1011-1013, August 2011.
  13. S. C. Rustagi, N. Singh,W. W. Fang, K. D. Buddaraju, S. R. Omampuliyar,S. H. G. Teo, C. H. Tung G. Q. Lo, N. Balasubramanian, and D. L. Kwong,"CMOS inverter based on gate-all-around silicon- nanowire MOSFETs fabricated using top-down approach,"IEEE Electron Device Lett. ,vol. 28, no. 11, pp. 1021–1024,Nov. 2007.
  14. F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa," Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance,"IEEE Electron Device Lett. ,vol. EDL-8, no. 9, pp. 410–412, Sep. 1987.
  15. C. P. Auth and J. D. Plummer, "Scaling theory for cylindrical, fully depleted, surrounding- gate MOSFETs," IEEE Electron Device Lett. , vol. 18,no. 2, pp. 74–76, Feb. 1997.
  16. A. K. Sharma, S. H. Zaidi, S. Lucero, S. R. J. Brueck, and N. E. Islam, "Mobility and transverse field effects in channel conduction of wrap-around-gate nanowire MOSFETs,"Proc. Inst. Elect. Eng. -Circuits Device Syst. , vol. 151, no. 5, pp. 422– 430, Oct. 2004
  17. S. Y. Lee, S. -M. Kim, E. -J. Yoon, C. -W. Oh, I. Chung, D. Park, and K. Kim, "A novel multibridge-channel MOSFET (MBCFET): Fabrication technologies and characterization,"IEEE Trans. Nanotechnol. , vol. 2, no. 4, pp. 253–257, Dec. 2003.
  18. A. A. Hamoui and N. A. Rumin, "An analytical model for current, delay and poweranalysis of submicron CMOS logic circuits," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. , vol. 47, no. 10, pp. 999–1007, Oct. 2000.
  19. J. R. Hauser, " Noise margin criteria for digital logic circuits" IEEE Trans on Education, V 36, no. 4, Nov. 1993, pp. 363-368.
  20. B. A. Rainey, B. M. Fried, M. Ieong, J. Kedzierski, E. J. Nowak,"Demonstration of FinFET CMOS circuits", IEEE Dev Res. Conf. Proc. , 2002, pp. 47-48.
  21. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C-Y Yang, C. Tabery, C. Ho, Q. Xiang, T-J King, J. Bokor, C. Hu, M-R Lin and D. Kyser,"FinFET scaling to 10nm gate length", in IEDM Tech. Dig. , 2002, pp. 251-254
Index Terms

Computer Science
Information Sciences

Keywords

Gate-All-Around (GAA) silicon nanowire Drain induced barrier lowering (DIBL) Metal oxide semiconductor field effect transistor (MOSFET)

Powered by PhDFocusTM