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Design of Efficient Reversible Multiply Accumulate (MAC) Unit

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International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 85 - Number 16
Year of Publication: 2014
Authors:
Rangaraju H G
Arpitha H S
Muralidhara K N
10.5120/14922-3338

Rangaraju H G, Arpitha H S and Muralidhara K N. Article: Design of Efficient Reversible Multiply Accumulate (MAC) Unit. International Journal of Computer Applications 85(16):1-12, January 2014. Full text available. BibTeX

@article{key:article,
	author = {Rangaraju H G and Arpitha H S and Muralidhara K N},
	title = {Article: Design of Efficient Reversible Multiply Accumulate (MAC) Unit},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {85},
	number = {16},
	pages = {1-12},
	month = {January},
	note = {Full text available}
}

Abstract

The multiplication and accumulation are the vital operations involved in almost all the Digital Signal Processing applications. Consequently, there is a demand for high speed processors having dedicated hardware to enhance the speed with which these multiplications and accumulations are performed. In the present conventional circuits, the multiply accumulate unit multiplies the two operands, adds the product to the previously accumulated result and stores back the new result in the accumulator all in a single clock cycle. On the other hand, using reversible logic the implementation of digital circuits is gaining popularity with the arrival of quantum computing and reversible logic. In this paper, a novel reversible multiply accumulate unit is proposed. the comparison of various possible implementations of the reversible multiply accumulate unit in terms of gate count, quantum cost, constant inputs and number of garbage outputs is carried out.

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