CFP last date
22 April 2024
Reseach Article

Enhancing Data Fetching Rates with Parallel Pipelines

by Y. Narasimha Rao, G. Samuel Varaprasada Raju
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 85 - Number 6
Year of Publication: 2014
Authors: Y. Narasimha Rao, G. Samuel Varaprasada Raju
10.5120/14848-3208

Y. Narasimha Rao, G. Samuel Varaprasada Raju . Enhancing Data Fetching Rates with Parallel Pipelines. International Journal of Computer Applications. 85, 6 ( January 2014), 31-34. DOI=10.5120/14848-3208

@article{ 10.5120/14848-3208,
author = { Y. Narasimha Rao, G. Samuel Varaprasada Raju },
title = { Enhancing Data Fetching Rates with Parallel Pipelines },
journal = { International Journal of Computer Applications },
issue_date = { January 2014 },
volume = { 85 },
number = { 6 },
month = { January },
year = { 2014 },
issn = { 0975-8887 },
pages = { 31-34 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume85/number6/14848-3208/ },
doi = { 10.5120/14848-3208 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:01:48.155639+05:30
%A Y. Narasimha Rao
%A G. Samuel Varaprasada Raju
%T Enhancing Data Fetching Rates with Parallel Pipelines
%J International Journal of Computer Applications
%@ 0975-8887
%V 85
%N 6
%P 31-34
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In the present techno-world parallel computers are playing vital role in information exchange through various media such as internet and other electronic media. It is very important to consider the data speed along with success rate. The information should reach the destination in time than it become too late. In the present paper, pipeline technologies are discussed to improve data rates. In the present paper two linear pipelines are connected in parallel to improve the fetching speed of the processor. The two pipelines are synchronized and controlled alternatively with common clock pulse.

References
  1. IEEE and José G. Delgado-Frias, Senior Member, IEEE,A Mesychronous high performance digital systems, VOL. 53, NO. 5, MAY 2006
  2. Thomas gay, ?Timing constraints for wave pipelined systems? IEEE transactions on Computer aided design of integrated circuits, vol13, no. 8, august 1994
  3. JabulaniNyathi, ?A high performance hybrid wave pipelined linear feedback shift register with skew tolerant clocks?, IEEE, 1384- 1387, 2004
  4. Mohammad Maymandi, ?A digital programmable delay element: Design and analysis?, IEEE transaction VLSI systems, Vol. 11, no. 5, October 2003
  5. Wayne P. Burleson, ?Wave-Pipelining: A Tutorial and Research Survey?, IEEE Transactions on very large scale integration (vlsi) systems, vol. 6, no. 3, september 1998
  6. L. Cotten, ?Maximum rate pipelined systems,? in Proc. AFIPS Spring Joint Comput. Conf. , 1969.
  7. Eby G. Friedman, ?Clock Distribution Networks in Synchronous Digital Integrated Circuits?, Invited paper, Proceedings of the ieee, vol. 89, no. 5, may 2001 pp665.
  8. http://www. ece. rochester. edu/users/friedman/papers/Wiley_99_CDN. pdf
  9. Suryanarayana B. Tatapudi et al. , http://www. ece. rochester. edu/users/friedman/papers/Wiley_99_CDN. pdf
Index Terms

Computer Science
Information Sciences

Keywords

pipeline data rates parallelism parallel pipeline