CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

Verification of Asynchronous FIFO using System Verilog

by Amit Kumar, Shankar, Neeraj Sharma
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 86 - Number 11
Year of Publication: 2014
Authors: Amit Kumar, Shankar, Neeraj Sharma
10.5120/15029-3347

Amit Kumar, Shankar, Neeraj Sharma . Verification of Asynchronous FIFO using System Verilog. International Journal of Computer Applications. 86, 11 ( January 2014), 16-20. DOI=10.5120/15029-3347

@article{ 10.5120/15029-3347,
author = { Amit Kumar, Shankar, Neeraj Sharma },
title = { Verification of Asynchronous FIFO using System Verilog },
journal = { International Journal of Computer Applications },
issue_date = { January 2014 },
volume = { 86 },
number = { 11 },
month = { January },
year = { 2014 },
issn = { 0975-8887 },
pages = { 16-20 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume86/number11/15029-3347/ },
doi = { 10.5120/15029-3347 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:03:56.722962+05:30
%A Amit Kumar
%A Shankar
%A Neeraj Sharma
%T Verification of Asynchronous FIFO using System Verilog
%J International Journal of Computer Applications
%@ 0975-8887
%V 86
%N 11
%P 16-20
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

As the designs gets complex, the probability of occurrence of bugs increases. This necessitated the introduction of the verification phase for verifying the functionality of the IC and to detect the bugs at an early stage. In this paper, the Asynchronous FIFO design is verified using SystemVerilog. The design uses a grey code counter to address the memory and for the pointer.

References
  1. Mohit Arora, "The Art of Hardware Architecture: Design Methods and Techniques for Digital Circuits," Springer, 2011, ch 3, sec 3. 3, pp 54-55
  2. Clifford E. Cummings, "Simulation and Synthesis Techniques for Asynchronous FIFO Design," SNUG 2000 Users Group Conference, San Jose, CA, 2002) User Papers, March 2002.
  3. Clifford E. Cummings, "Synthesis and Scripting Techniques for Designing Multi-Asynchronous Clock Designs," SNUG 2001 (Synopsys Users Group Conference, San Jose, CA, 2001) User Papers, March 2001
  4. Clifford E. Cummings and Don Mills, "Synchronous Resets? Asynchronous Resets? I am So Confused! How Will I Ever Know Which to Use?" SNUG 2002 (Synopsys Users Group Conference, San Jose, CA, 2002) User Papers, March 2002.
  5. Dadhania Prashant C. "Designing Asynchronous FIFO," Journal Of Information, Knowledge and Reseaarch In Electronics and communication Engineering, Vol. 2, Issue. 2, November 2013
  6. Chris Spears, "System Verilog for Design, "A Guide to Using System Verilog for Hardware Design and Modeling," Springer Second edition.
  7. Mu-Tien Chang, Po-Tsang Huang, and Wei Hwang,"A Robust Ultra-Low Power Asynchronous FIFO Memory with Self-Adaptive Power Control," SOC Conference, 2008 IEEE International, pp. 175-178, Sept. , 2008
Index Terms

Computer Science
Information Sciences

Keywords

Asynchronous FIFO Setup time Hold time Metastability Verification

Powered by PhDFocusTM