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Design and Analysis of Dual Edge Triggered D Flip-Flop
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 90 - Number 16 |
| Year of Publication: 2014 |
| Authors: Sukanya.t, Sathiskumar.m, Akila.m |
10.5120/15808-4563
|
Sukanya.t, Sathiskumar.m, Akila.m . Design and Analysis of Dual Edge Triggered D Flip-Flop. International Journal of Computer Applications. 90, 16 ( March 2014), 38-46. DOI=10.5120/15808-4563
Abstract
Power consumption and energy efficiency plays a vital role in sequential circuit design. Clock gating is a technique that is used to reduce the dynamic power consumption of idle modules. Usage of Dual Edge Triggered Flip-flop (DETFF) is an efficient technique since it consumes half the clock frequency and less power than Single Edge Triggered Flip-flops (SETFF's). Integrating clock gating technique with DETFF reduces the power consumption further, but it leads to asynchronous data sampling problem (change in output between clock edges). In this paper, two methods have been used to eradicate asynchronous data sampling problem and their power analysis has been estimated. In order to reduce the power consumption further, a new design has been proposed for DETFF. Based on the new design, two methods have been implemented using Tanner EDA tool. The performance comparison is made using CMOS 0. 18µm technology.
References
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- Xiaowen Wang and William H. Robinson, (2013) "Asynchronous Data Sampling Within Clock-Gated Dual Edge Triggered Flip-Flops". IEEE Transactions on Circuits and Systems—I: Regular Papers, Vol. 60, pp 2401-2411.
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