CFP last date
20 May 2024
Call for Paper
June Edition
IJCA solicits high quality original research papers for the upcoming June edition of the journal. The last date of research paper submission is 20 May 2024

Submit your paper
Know more
The week's pick
Responsive image
Enhancing Privacy Preservation: Multi-Attribute Protection with P-Sensitive K-Anonymity

Twinkle Patel Kiran Amin
Random Articles
Reseach Article

Reversible Architecture of Computer Arithmetic

by Sayeeda Sultana, Katarzyna Radecka
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 93 - Number 14
Year of Publication: 2014
Authors: Sayeeda Sultana, Katarzyna Radecka
10.5120/16281-5852

Sayeeda Sultana, Katarzyna Radecka . Reversible Architecture of Computer Arithmetic. International Journal of Computer Applications. 93, 14 ( May 2014), 6-14. DOI=10.5120/16281-5852

@article{ 10.5120/16281-5852,
author = { Sayeeda Sultana, Katarzyna Radecka },
title = { Reversible Architecture of Computer Arithmetic },
journal = { International Journal of Computer Applications },
issue_date = { May 2014 },
volume = { 93 },
number = { 14 },
month = { May },
year = { 2014 },
issn = { 0975-8887 },
pages = { 6-14 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume93/number14/16281-5852/ },
doi = { 10.5120/16281-5852 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:15:42.840861+05:30
%A Sayeeda Sultana
%A Katarzyna Radecka
%T Reversible Architecture of Computer Arithmetic
%J International Journal of Computer Applications
%@ 0975-8887
%V 93
%N 14
%P 6-14
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Reversible logic plays an important role in emerging low power designs and quantum computing. This paper presents an efficient way to realize reversible arithmetic circuits especially targeting toward reversible arithmetic logic unit (RALU). In literature for reversible logic, not a significant advancement is found in integrating both logical and arithmetical functions, commonly known as arithmetic logic unit (ALU), a key feature of any computing system architecture. Here, this work presents a novel reversible arithmetic logic unit (ALU) performing basic functions similar to classical ALU such as addition, subtraction, AND, OR and XOR operations. Additional functions such as, NAND, NOR, XNOR and logical functions with single input inverted, overflow detection and comparison can also be performed with this design. The integration of these operations in single module using less number of control signals is not available in any of existing approaches. The design and analysis based on different parameters of reversible circuits – number of gates, garbage bits and quantum cost as well as simulation results are presented here. The proposed design offers efficient programmability and more flexibility than other methods.

References
  1. R. Landauer, "Irreversibility and heat generation in the computational process". IBM Journal of Research and Development, 1961. 5(3): pp. 183-191.
  2. C. H. Bennett, "Logical reversibility of computation", IBM Journal of Research and Development, 1973. 17(6): pp. 525-532.
  3. M. A. Nielsen, I. L. Chuang, "Quantum Computation and Quantum Information", Cambridge University Press, 2000.
  4. W. C. Athas and L. J. Svensson, "Reversible Logic Issues in Adiabatic CMOS", Workshop on Physics and Computation, 1994, pp. 111-118.
  5. S. Burignat and A. D. Vos, "Test of a Majority-based Reversible (Quantum) 4-bits Ripple Carry Adder in Adiabatic Calculation", 18th International Conference on Mixed Design of Integrated Circuits and Systems, 2011, pp. 368-373.
  6. H. Thapliyal and M. Zwolinski, "Reversible Logic to Cryptographic Hardware: a New Paradigm", CoRRabs/cs/0610089, 2006.
  7. H. Thapliyal and N. Ranganathan, "Mach-Zehnder interferometer based design of all optical reversible binary adder", Design, Automation and Test in Europe, 2012.
  8. M. Skoneczny, Y van Rentergem and A. D. Vos, "Reversible Fourier Transform Chip", 15th International Conference on Mixed Design of Integrated Circuits and Systems, 2008.
  9. A. D. Vos, S. Burignat and M. K. Thomsen, " Reversible Implementation of a discrete Integer Linear Transformation", Journal of Multiple-Valued Logic and Soft Computing, vol. 18, no. 1, pp. 25-35, 2012.
  10. D. Maslov, G. W. Dueck and D. M. Miller, "Techniques for the Synthesis of Reversible Toffoli Networks", ACM Trans. on Design Automation of Electronic System, Vol. 12, No. 4, pp. 42:1-42:28, Sept. 2007.
  11. D. Grobe, R. Wille, G. Dueck and R. Drechsler, "Exact Multiple Control Toffoli Network Synthesis with SAT Techniques", IEEE Trans. On CAD, vol. 28, no. 5, pp. 703-715, 2009.
  12. P. Gupta, A. Agrawal and N. K. Jha, "An Algorithm for Synthesis of Reversible logic Circuits", IEEE Trans. on CAD of Integrated Circuits and Sys. vol. 25, no. 11, 2006.
  13. V. Shende, A. K. Prasad, I. L. Markov, and J. P. Hayes. "Synthesis of reversible logic circuits", IEEE Trans. on CAD, 22(6):710–722, 2003.
  14. R. Wille, R. Drechsler," BDD-based Synthesis of Reversible logic for Large Functions" Design Automation Conf. , 2009.
  15. N. Alhagi, M. Hawash, M. A. Perkowski, "Synthesis of Reversible Circuits with No Ancilla Bits for Large Reversible Functions Specified with Bit Equations", Proc. of the 40th IEEE International Symp. on Multiple-Valued Logic, pp. 39-45, 2010.
  16. M. Saeedi and I. L. Markov, " Synthesis and Optimization of Reversible Circuits- A Survey", ACM Computing Surveys 2012.
  17. L. Ni, Z. Guan and W. Zhu, "A General method of Constructing the Reversible Full Adder", 3rd Intl. Symp. on Intelligent Inf. Technology and Security Informatics, pp. 109-113, 2010.
  18. H. Thapliyal and M. B Srinivas, "Novel Design and Reversible Logic Synthesis of Multiplexer Based Full Adder and Multipliers", 48th Midwest Symp. on Circuits and Systems, vol. 2, pp. 1593-1596, 2006.
  19. H. Thapliyal, M. B Srinivas, "Novel Reversible TSG gate and its application for designing reversible carry look ahead adder and other adder architectures", Proc. of 10th Asia-pacific computer system architecture Conference, 3740, 2005.
  20. M. Haghparast and K. Navi, "Design of a novel reversible multiplier circuit using HNG gate in nanotechnology", Am. J. Applied Sci. , vol. 5, 2008, 282.
  21. M. Ehsanpour, P. Moallem, A. Vafaei, "Design of a Novel Reversible Multiplier Circuit Using Modified Full Adder", 2010 Intl. Conf. on Computer Design and Applications, vol. 3 .
  22. H. Thapliyal, M. B Srinivas and H. R. Arabnia, "Reversible Logic Synthesis of Half, Full and Parallel Subtractors", Proc. of Intl. Conf. on embedded Sys. and App. , June 2005, Las Vegas, pp. 165-181.
  23. H. Thapliyal and N. Ranganathan, "Design of Efficient Binary Subtractors Based on a New Reversible Gate", Proc. of 2009 IEEE Computer Society Annual Symp. on VLSI, pp. 229-234.
  24. H. G. Rangaraju, U. Venugopal, K. N. Muralidhara and K. B. Raja, " Low Power Reversible Parallel Binary Adder/Subtractor", Intl. J. of VLSI design & Comm. Sys. (VLSICS), Vol. 1, no. 3, 2010, pp 23-34.
  25. V. Vedral, A. Barenco and A Ekert, " Quantum Networks for Elementary Arithmetic Operations", Phys. Rev. A, vol. 54, no. 1, pp. 147-153, 1996.
  26. S. A. Cuccaro, T. G. Draper, S. A. Kutin and D. P. Moulton, " A new Quantum Ripple-Carry Addition Circuit," quant-ph/0410184, 2004.
  27. Y. Takahashi, S. Tani and N. Kunihiro, " Quantum Addition Circuits and Unbounded Fan-out, " Quantum Information and Computation, vol. 10, no. 9&10, pp. 872-890, 2010.
  28. I. L. Markov and M. Saeedi, "Constant-Optimized Quantum Circuits for Modular Multiplication and Exponentiation", Quantum Information and Computation, vol. 1. no. 5&6, pp. 872-890, 2012.
  29. M. K. Thomsen, H. B. Axelsen and R. Gluck, " A Reversible Processor Architecture and its Reversible Logic Design", Reversible Computation, Lecture Notes in Computer Science, vol. 7165, 2012, pp 30-42.
  30. Benchmark circuits. http://www. revlib. org
  31. R. Aradhaya, K. N. Muralidhara, B. Kumar, " Design of Low Power Arithmetic Unit Based on Reversible Logic", International Journal of VLSI and Signal Processing Applications, vol. 1, no. 1, pp. 30-38, 2011.
  32. M. K. Thomsen, R. Gluck, H. B. Axelsen, "Reversible arithmetic logic unit for quantum arithmetic", J. Phys. A: Math. Theor. , vol. 43, no. 38, 2010.
  33. M. Morrison and N. Ranganathan, " Design of a Reversible ALU based on Novel Programmable Reversible Logic Gate Structures", IEEE Computer Society Annual Symposium on VLSI, 2011, pp. 126-131.
  34. T. Toffoli, " Reversible Computing", Technical Memo, MIT/LCS/TM-151, Boston 1980.
  35. E. Fredkin, T. Toffoli, "Conservative Logic", Int. J. Theor. Physics, vol. 21, no. 3-4, pp. 219-253, 1982.
  36. A. Peres, " Reversible logic and quantum computers," Phys. Rev. A, Gen. Phys. , vol 32, no. 6, pp. 3266-3276, Dec. 1985.
  37. S. Sultana, K. Radecka, " Reversible adder/subtractor with overflow detector", Intl. Midwest Symp. on Circuits and Systems (MWSCAS 2011), pages 1- 4.
  38. V. Carl Hamacher, Safwat G. Zaky and Zvonko G. Vranesic, Computer Organization" New York : McGraw-Hill, ©1984, ISBN: 0072320869.
  39. https://www. altera. com/download/software/quartus-ii-we/9.
Index Terms

Computer Science
Information Sciences

Keywords

Arithmetic logic unit Reversible logic Reversible controlled adder/subtractor Quantum cost.

Powered by PhDFocusTM