The week's pick
Random Articles
Reseach Article
A High Speed Explicit Pulsed Dual Edge Triggered D Flip Flop
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 93 - Number 17 |
| Year of Publication: 2014 |
| Authors: Manan Joshi, D S Chauhan, B. K. Kaushik |
10.5120/16425-5607
|
Manan Joshi, D S Chauhan, B. K. Kaushik . A High Speed Explicit Pulsed Dual Edge Triggered D Flip Flop. International Journal of Computer Applications. 93, 17 ( May 2014), 5-9. DOI=10.5120/16425-5607
Abstract
This paper presents an efficient explicit pulsed static dual edge triggered flip flop with an improved performance. The proposed design overcomes the drawbacks of the dynamic logic family and uses explicit clock pulse generator approach to achieve dual edge triggering. The proposed flip-flop is compared with existing explicit pulsed dual edge triggered flip-flops. Based on the simulation results overall improvements of 12. 67% and 10. 15% are observed in delay and power delay product respectively.
References
- N. Nedovic, and V. G. Oklobdzija, "Dual Edge Triggered Storage Elements and Clocking Strategy for Low Power Systems," IEEE Trans. VLSI Systems, vol. 13, no. 5, pp 577-590, May 2005.
- Q. Huang, and R. Rogenmoser, "Speed Optimisation of Edge-Triggered CMOS Circuits for Gigahertz Single-Phase Clocks," IEEE J. Solid-State Circuits, vol. 31, no. 3, Mar. 1996.
- B. Nicolic, V. G. Oklobdzija, V Stojanovic, W. Jia, J. K. S. Chiu, and M. M. T. Leung, "Improved Sense-Amplifier-Based Flip Flop: Design and Measurements," IEEE J. Solid-State Circuits, vol. 35, no. 6, June 2000.
- B. S. Kong, S. S. Kim, and Y. H. Jun, "Conditional-Capture Flip Flop for Statistical Power Reduction," IEEE J. Solid-State Circuits, vol. 36, no. 8, Aug. 2001.
- C. Kim, and S. M. Kang "A Low Swing Clock Double-Edge Triggered Flip Flop", IEEE J. Solid-State Circuits, vol. 37, no. 5, May 2002.
- P. Zhao, T. K. Darwish, and M. A. Bayoumi, "High-Performance and Low-Power Conditional Discharge Flip Flop," IEEE Trans. VLSI Systems, vol. 12, no. 5, May 2004.
- C. K. The, M. Hamada, T. Fujita, H. Hara, N. Ikumi, and Y. Oowaki, "Conditional Data Mapping Flip Flops for Low Power and High Performance Systems," IEEE Trans. VLSI Systems, vol. 14, no. 12, Dec. 2006.
- P. Zhao, J. M. Neely, P. Golconda, M. A. Bayoumi, R. A. Barcenas, and W. Kuang, "Low Power Clock Branch Sharing Double Edge Triggered Flip Flop," IEEE Trans. VLSI systems, vol. 15, no. 7, July 2007.
- P. Zhao, J. B. McNealy, P. K. Golconda, S. Venigalla, M. A. Bayoumi, W. Kuang, and L. Downey, "Low Power Clocked Pseudo NMOS Flip Flop for level Conversion in Dual Supply Systems," IEEE Trans. VLSI Systems, vol. 17, no. 9, Sept. 2009.
- L. Y. Chiou, and S. C. Luo, "Energy Efficient Dual Edge Triggered Level Converting Flip Flops with Symmetry in Setup Times and Insensitivity to Output Parasitics," IEEE Trans. VLSI Systems, vol. 17, no. 11, Nov. 2009.
- M Alioto, E Consoli, and G Palumbo, "Analysis and Comparison in the Energy-Delay-Area domain of nanometer CMOS flip flops: Part II - Results and Figures of Merit," IEEE Trans. VLSI Systems, vol. 19, No. 5, May 2011.
- X. X. Wu, and J. Z. Shen, "Low power explicit-pulsed triggered flip flop with robust output," Electronic Letters, vol. 48, no. 24, Nov. 2012.
- M. W. Phyu, W. L. Goh, and K. . S. Yeo, "A low-power static dual edge triggered flip–flop using an output-controlled discharge configuration," IEEE Int. Symp. on Circuits and Systems, Japan, May 2005, Vol. 3, pp. 2429–2432.
- Y. Dai, and J. Shen, "Structure and design method for pulse triggered flip–flops at switch level," J. Cent. South Univ. Technol. , vol. 17, no. 6, pp. 1279–1284, 2010.
- N. Lotze, and Y Manoli, "A 62mV 0. 13µm CMOS Standard-Cell-Based Design Technique using Schmitt Trigger Logic," IEEE J. Solid-State Circuits, vol. 47, no. 1, Jan. 2012.
- S. Lutkemeir, T. Jungeblut, H. K. O. Burge, S. Aunet, M. Porrmann, and U. Ruckert, "A 65nm 32b Subthreshold Processor with 9T multi Vt SRAM and adaptive supply voltage control," IEEE J. Solid-State Circuits, vol 48, no 1, Jan 2013.
- W. Chung, T. Lo, and M. Sachdev, "A Comparative Analysis of Low-Power Low Voltage Dual-Edge Triggered Flip Flops," IEEE Trans. VLSI Systems, vol. 10, no. 6, Dec. 2002.
- R. Zimmermann, and W. Fichtner, "Low Power Logic Styles: CMOS versus Pass-Transistor Logic," IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079-1090, July 1997.
- O. Sarbishei, and M. M. Nejad, "A Novel Overlap based Logic Cell: An Efficient Implementation of Flip Flops with embedded Logic," IEEE Trans. VLSI Systems, vol. 18, no. 2, Feb. 2010
- J. B. A. Constantino, and J. A. R. Madamba, "Static dual edge flip flop implementations on the 90nm process," in Proc. IEEE 2011, 5th Asia Modelling Symp.
Index Terms
Keywords