CFP last date
20 May 2024
Reseach Article

ADA: Applications Define ASIP

by Manoj Kumar Jain
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 95 - Number 14
Year of Publication: 2014
Authors: Manoj Kumar Jain
10.5120/16663-6650

Manoj Kumar Jain . ADA: Applications Define ASIP. International Journal of Computer Applications. 95, 14 ( June 2014), 25-28. DOI=10.5120/16663-6650

@article{ 10.5120/16663-6650,
author = { Manoj Kumar Jain },
title = { ADA: Applications Define ASIP },
journal = { International Journal of Computer Applications },
issue_date = { June 2014 },
volume = { 95 },
number = { 14 },
month = { June },
year = { 2014 },
issn = { 0975-8887 },
pages = { 25-28 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume95/number14/16663-6650/ },
doi = { 10.5120/16663-6650 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:19:28.023244+05:30
%A Manoj Kumar Jain
%T ADA: Applications Define ASIP
%J International Journal of Computer Applications
%@ 0975-8887
%V 95
%N 14
%P 25-28
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Interest in Application Specific Instruction set Processors or ASIPs has increased significantly. Sincere efforts have been put in improving ASIP design methodologies in industry as well as in academia. By the close observation and analysis of these approaches, it was found that though the existing approaches are focusing on making the process automatic and providing better GUI to help the designers, core technique used in deciding the suitable architecture (processor and memory) is based on design space exploration. This exploration is done with the help of estimators. Such estimators are either simulator based or scheduler based. This study identifies that both types of techniques are very far from the ideal dream technique in which applications should have defined the suitable architecture configuration and these techniques are becoming unsuitable in current scenario. Each problem has a solution hidden in it. This scenario motivated us to propose a novel and revolutionary ASIP design technique making the dream true. The Proposed technique does not focuses on design space exploration, it focuses on directly defining processors for given applications rather than searching for suitable configuration in a jungle of configurations can be suggested by the architecture design space.

References
  1. Jain M. K. , Balakrishnan M. , and Kumar A. , 2001, "ASIP Design Methodologies: Survey and Issues", In Proceedings of the IEEE/ ACM International Conference on VLSI Design. (VLSI 2001), pages 76-81.
  2. Gour Deepak, Jain M. K. , 2011, "ASIP Design Space Exploration: Survey and Issues", International Journal of Computer Science and Information Security, Vol. 9, No. 3, 2011, pages: 141-145.
  3. Jain M. K. , and Gour Deepak, 2012, "Comparison between the Simulator and Scheduler based approach of Design Space Exploration for Application Specific Instruction set Processor", International Journal of Computer Applications, IJCA, ISSN: 0975-5887, Vol. 43, No. 5, April 2012, Pages 14-19.
  4. Halambi A. , Grun P. , Khare A. , Ganesh V. , Dutt N. , Nicolau A,, 1999, "EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability", In Proceedings of the Design Automation and Test in Europe (DATE), March 1999, pages 485–490.
  5. Pees S. , Zivojnovic V. , Meyr H. , 1999, "LISA- Machine Description Language for Cycle Accurate Models of Programmable DSP Architectures", In Proceedings of the Design Automation Conference (DAC), June 1999, pages 933–938.
  6. Hoffmann A. , Kogel T. , Nohl A. , Braun G. , O. Schliebusch O. , Wahlen O. , Wieferink A. , Meyr H. , 2001, "A Novel Methodology for the Design of Application-Specific Instruction-Set Processors (ASIPs) Using a Machine Description Language", In IEEE Transactions on Computer Added Design of Integrated Circuits and Systems, 20(11), November 2001, pages 1338–1354.
  7. Radhakrishnan S. , 2006, "Customization of application specific heterogeneous multi pipeline processors", In Proc. EDAA 2006, pp. 746 – 751.
  8. Yoonjin Kim, Mary Kiemb, Kiyoung Choi, 2005, "Efficient Design Space Exploration for Domain-Specific Optimization of Coarse-Grained Reconfigurable Architecture", In Design, Automation and Test in Europe, 2005. Proceedings, 7-11 March 2005, page(s): 12 – 17.
  9. Bossuet L. , Gogniat G. , and Philippe J. L. , "Communication-Oriented Design Space Exploration for Reconfigurable Architectures", In EURASIP Journal on Embedded Systems, Volume 2007, Article ID 23496.
  10. Pasricha S. , and Dutt N. , "A Framework for Memory and Communication Architecture Co-synthesis in MPSoCs", In Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 26, Issue 3, March 2007 Page(s):408 – 420.
  11. Kenshu Seto and Masahiro Fujita, "Custom instruction generation for configurable processors with limited numbers of operands", IPSJ Transactions on System LSI Design Methodology Vol. 3, 57-68, Feb 2010.
  12. Jain M. K. , and Ramnani V. , 2013, "Design Space Exploration for a Custom VLIW architecture", International Journal of Computer Applications, IJCA, ISSN: 0975-5887, Vol. 61, No. 8, January 2013, Pages: 31-34.
  13. Tensilica Inc. , http://www. tensilica. com.
  14. Altera Corp. , http://www. altera. com.
  15. Xilinx Inc. , http://www. xilinx. com
  16. Gupta T. V. K. , Sharma P. , Balakrishnan M. , Malik S. , 2000, "Processor evaluation in an embedded systems design environment", In Proc. VLSI Design 2000, pages 98-103, January 2000.
  17. Jain M. K. , Balakrishnan M. , and Kumar A. , 2002, "An Efficient Technique for Exploring Register File Size in ASIP Design", IEEE TCAD, Vol. 23, Issue 12, December 2004. Pages: 1693-1699.
  18. Jain M. K. , Balakrishnan M. , and Kumar A. , 2003, "Exploring Storage Organization in ASIP Synthesis", In Digital System Design, 2003. Proceedings. Euromicro Symposium, 1-6 Sept. 2003, pages: 120 – 127.
  19. Jain M. K. , 2011, "A Multi Layer Technique for Performance Estimation for ASIP Design Space Exploration", International Journal of Advanced Research in Computer Science, IJARCS, Vol. 2, No. 4, August 2011, Pages 648-653.
  20. Jain M. K. , Balakrishnan M. , and Kumar A. , 2005, "Integrated On-chip Storage Evaluation in ASIP Synthesis", Proceedings of the IEEE Eighteenth International Conference on VLSI Design with Fourth International Conference on Embedded System Design, VLSI 2005, 3-7 January, 2005, pages: 274-279.
Index Terms

Computer Science
Information Sciences

Keywords

Application Specific Instruction Set Processor (ASIP) Embedded System Design Real-time systems Design Space Exploration.