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Built in Self-Test for 4 × 4 Signed and Unsigned Multipliers in FPGA
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 95 - Number 16 |
| Year of Publication: 2014 |
| Authors: Shrikant Vaishnav, Puran Gaur, Braj Bihari Soni |
10.5120/16681-6792
|
Shrikant Vaishnav, Puran Gaur, Braj Bihari Soni . Built in Self-Test for 4 × 4 Signed and Unsigned Multipliers in FPGA. International Journal of Computer Applications. 95, 16 ( June 2014), 30-35. DOI=10.5120/16681-6792
Abstract
Built in self-test (BIST) is a technique or a method which allow the circuit to test itself. BIST increases the controllability and observability of integrated circuit therefore it is easier to apply inputs and then detect faults from it [11]. BIST also decreases the time of testing integrated circuits & gives very high fault coverage. Therefore in many ways BIST help us in detecting fault in integrated circuits. This paper presents an efficient fault detection algorithm for 4 × 4 signed & unsigned multiplier in field programmable gate array (FPGA). These techniques were successfully applied on booth, braun & unsigned array multipliers.
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