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Reconfigurable CPL Adiabatic Gated Logic –RCPLAG based Universal NAND/NOR Gate

International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 95 - Number 26
Year of Publication: 2014
Manoj Sharma
Arti Noor

Manoj Sharma and Arti Noor. Article: Reconfigurable CPL Adiabatic Gated Logic RCPLAG based Universal NAND/NOR Gate. International Journal of Computer Applications 95(26):27-32, June 2014. Full text available. BibTeX

	author = {Manoj Sharma and Arti Noor},
	title = {Article: Reconfigurable CPL Adiabatic Gated Logic RCPLAG based Universal NAND/NOR Gate},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {95},
	number = {26},
	pages = {27-32},
	month = {June},
	note = {Full text available}


In precursory efforts authors have illustriously consolidated the benefits of CPL based circuits and adiabatic logic conjoint the use of clock for even combinational blocks and reported the power diminution. With the adhibition of clock in combinational blocks, the same circuit topology may be employed for sequential behavior as manifested by authors in their erstwhile works. Proceeding forward in the same direction and augmenting another edge into this, authors have reported the reconfigurable circuit implementation utilizing the reported CPLAG concepts. In pursuance of the same authors have contemplated and implemented reconfigurable 'Nand' and 'Nor' gates. The same circuit topology can be used for either functionality governed by a control signal. The functional behavior of the circuit realized for 'Nand' and 'Nor' are analyzed and found to be cogent. The power results shows improvement by 4-5% as compared to SCMOS based circuits. The proposed RCPLAG universal gate is investigated for different voltage levels and transistor size. The parameters like power dissipation, power fed back to system, Trise, Tfall, propagation delays, PDP are further examined and found to be satisfactory. The best operating conditions for the said circuit lies in voltage range of less than 2. 5V. The Pavg at 1V, 180nm technology is 12. 2nW with 36f units PDP, 5µs maximum delay.


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