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True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique

International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 96 - Number 11
Year of Publication: 2014
Priyanka Sharma
Rajesh Mehra

Priyanka Sharma and Rajesh Mehra. Article: True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique. International Journal of Computer Applications 96(11):44-51, June 2014. Full text available. BibTeX

	author = {Priyanka Sharma and Rajesh Mehra},
	title = {Article: True Single Phase Clocking Flip-Flop Design using Multi Threshold CMOS Technique},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {96},
	number = {11},
	pages = {44-51},
	month = {June},
	note = {Full text available}


This paper enumerates the design of low power and high speed double edge triggered True Single Phase Clocking (TSPC) D- flip-flop. The TSPC CMOS flip-flop uses only one clock signal that is never inverted and it eliminates the clock skew. The originally developed TSPC flip-flop are very sensitive to the clock slope and large portion of power is spent in pre-charging the internal nodes, which makes TSPC dynamic circuits less power efficient. In the conventional CMOS design, high leakage current is becoming a significant contributor to power dissipation. To overcome the existing problem of CMOS TSPC D flip-flop, a Multi-threshold CMOS (MTCMOS) technology is used for leakage minimization. The designed flip-flops are compared in terms of power consumption and propagation delay and power delay product and simulations are carried out by MICROWIND 3. 1 tools. The proposed MTCMOS designs such as original MTCMOS implmentation and NMOS insertion in MTCMOS design of TSPC D flip-flop saves static power 57. 517% and 58. 871% as compared to conventional DE-TSPC D flip-flop respectively at 1. 2V.


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