Call for Paper - January 2023 Edition
IJCA solicits original research papers for the January 2023 Edition. Last date of manuscript submission is December 20, 2022. Read More

Hardware Acceleration of Hamming Code: Design of Runtime Reconfigurable FPGA Prototype

Print
PDF
International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 96 - Number 14
Year of Publication: 2014
Authors:
Rohit Jain
Praddumna Deshpande
Pournima Shah
10.5120/16862-6750

Rohit Jain, Praddumna Deshpande and Pournima Shah. Article: Hardware Acceleration of Hamming Code: Design of Runtime Reconfigurable FPGA Prototype. International Journal of Computer Applications 96(14):14-21, June 2014. Full text available. BibTeX

@article{key:article,
	author = {Rohit Jain and Praddumna Deshpande and Pournima Shah},
	title = {Article: Hardware Acceleration of Hamming Code: Design of Runtime Reconfigurable FPGA Prototype},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {96},
	number = {14},
	pages = {14-21},
	month = {June},
	note = {Full text available}
}

Abstract

Digital communications has helped us achieve two way conversations in digital domain, in which messages are encoded into the communication channel and then decoded at the receiver end. During the transfer of message, the data might get corrupted due to disturbances in the communication channel. Hence, it is necessary that the decoder has an in-built function of detecting and correcting the errors that might occur. This project deals with channel coding with an objective of error correction and detection using a forward error correction algorithm viz. Hamming Code, which is basically a linear block code. The implementation of this code is done on ACTEL-ProASIC3 FPGA (250Kgates), and programmed in VHDL. The HDL entry is made in LIBERO-IDE CAD tool , Synplify tool is used for synthesis, Netlist Viewer for generation of Netlists and Timer for Static Timing Analysis. The unit testing of each module and integration testing of the system is performed by simulation in MODELSIM 6. 6d and by actual hardware implementation on Actel ProASIC3 FPGA. The code rate achieved here is 57. 1%. FPGA is preferred over microcontroller development boards because variable frequency and dedicated pathways comprised of programmable logic blocks in FPGA's allow high speed implementation of large data streams. The aim of this project is to implement a semiconductor IP Core. The FPGA Prototype we designed serves as a predecessor for ASIC.

References

  • Datasheet of Actel ProASIC 3 A3P250
  • Circuit design with VHDL by V. Pedroni
  • Circuit simulation and design with VHDL by V. Pedroni
  • VHDL Primer by J. Bhaskar
  • Digital system design using VHDL by Charles Roth
  • Fundamentals of Digital Logic Design with VHDL by Brown and Vrasenic
  • Computer Networks by Tanenbaum 5th Edition
  • Data Communications and Networking by Behrouz Forouzan
  • Prof. Rashmi Sinha, Novel Hamming code for error correction and detection of higher data bits using VHDL Intl Jrnl of Scientific & Engg Research, Vol 4, Iss 4, April-2013 272 ISSN 2229-5518
  • Tongsheng Zhang, Qun Ding, Design of (15, 11) Hamming Code Encoding and Decoding System Based on FPGA, Intl Conf On Instmn, Measmnt Comp, Comm & Contl 2011
  • Nutan Shep, P. H. Bhagat, Implementation of Hamming code using VLSI,Intl Jrnl of Engg Trnds & Tech Vol4, Iss2–2013
  • Brajesh Kumar Gupta, Prof. Rashmi Sinha, Various Methodologies used for 25 Bit Information Data String Communication through Hamming Code, Intl Jrnl of Appld Info Systms ISSN: 2249-0868
  • Leena, Subham Gandhi, Jitender Khurana, Implementation of (7, 4) Hamming Code on CPLD, Intl Jrnl of Engg Research & Tech ISSN: 2278-0181
  • Varun Jindal, Design of Hamming Code using Verilog VHDL, Magazine : Electronics For You February 2006