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Hardware Acceleration of Hamming Code: Design of Runtime Reconfigurable FPGA Prototype

International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 96 - Number 14
Year of Publication: 2014
Rohit Jain
Praddumna Deshpande
Pournima Shah

Rohit Jain, Praddumna Deshpande and Pournima Shah. Article: Hardware Acceleration of Hamming Code: Design of Runtime Reconfigurable FPGA Prototype. International Journal of Computer Applications 96(14):14-21, June 2014. Full text available. BibTeX

	author = {Rohit Jain and Praddumna Deshpande and Pournima Shah},
	title = {Article: Hardware Acceleration of Hamming Code: Design of Runtime Reconfigurable FPGA Prototype},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {96},
	number = {14},
	pages = {14-21},
	month = {June},
	note = {Full text available}


Digital communications has helped us achieve two way conversations in digital domain, in which messages are encoded into the communication channel and then decoded at the receiver end. During the transfer of message, the data might get corrupted due to disturbances in the communication channel. Hence, it is necessary that the decoder has an in-built function of detecting and correcting the errors that might occur. This project deals with channel coding with an objective of error correction and detection using a forward error correction algorithm viz. Hamming Code, which is basically a linear block code. The implementation of this code is done on ACTEL-ProASIC3 FPGA (250Kgates), and programmed in VHDL. The HDL entry is made in LIBERO-IDE CAD tool , Synplify tool is used for synthesis, Netlist Viewer for generation of Netlists and Timer for Static Timing Analysis. The unit testing of each module and integration testing of the system is performed by simulation in MODELSIM 6. 6d and by actual hardware implementation on Actel ProASIC3 FPGA. The code rate achieved here is 57. 1%. FPGA is preferred over microcontroller development boards because variable frequency and dedicated pathways comprised of programmable logic blocks in FPGA's allow high speed implementation of large data streams. The aim of this project is to implement a semiconductor IP Core. The FPGA Prototype we designed serves as a predecessor for ASIC.


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