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Design of High Speed Full Adder using Improved Differential Split Logic Technique for 130nm Technology and its Implementation in making ALU
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 96 - Number 18 |
| Year of Publication: 2014 |
| Authors: Gurleen Kaur, Arvind Kumar, Jatinder Singh |
10.5120/16898-6952
|
Gurleen Kaur, Arvind Kumar, Jatinder Singh . Design of High Speed Full Adder using Improved Differential Split Logic Technique for 130nm Technology and its Implementation in making ALU. International Journal of Computer Applications. 96, 18 ( June 2014), 40-47. DOI=10.5120/16898-6952
Abstract
Adders are the main components in digital designs which are used not only for addition but can be used for multiplication and division too. Adders find use in very large scale integrated circuits from processors (like in arithmetic logic circuits) to application specific integrated circuits. At the same time, high speed computation has become the important part of any digital applications today though low power is a key factor too. In this paper, a high speed full adder using improved differential split logic (DSL) technique is used. We further implement it in 1bit arithmetic logic circuit (ALU). Measurements show that proposed full adder is better than DSL full adder in terms of speed, and further implementation of it in ALU shows that it is better than CMOS ALU in terms of speed, power and power delay product (PDP).
References
- A. P. Chandrakasan, S. Sheng and R. W. Brodersen, "Low Power CMOS Digital Design," IEEE Journal of Solid-state Circuits, vol. 27, No. 4, pp. 473-484, April 1999.
- Dimtrios Soudris,Christian Piguet,Costas Goustis, "Designing CMOS Circuits for Low Power (European Low-Power Initiative for Electronic System Design (Series))" ,Kluwer Academic Publishers,Oct 2002,pp. 74-7t8
- P. Sheridan,C. M. Huizer,"AnExpression for the propagation delay of a Differential Split-Level (DSL) CMOS Logic Gate",IEEE Journal of solid state circuits,Vol-22,No. 3, June1987,pp. 457-459
- Leo C. M. G. Pfennings,Etal. ,"Differential Split Level CMOS Logic for Subnanosecond Speeds," IEEE Journal of Solid State Circuits, Vol. SC-20, No. 5, Oct 1985,pp. 1050-1055.
- Didem Z. Turker, Sunil P. Thakur, Edgar Sánchez-Sinencio ,"A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications", IEEE Transactions on circuits and systems-I:Regular papers, June 2011, Vol. 58, No. 6,pp. 1225-1238
- S. M. Aziz, W. A. J. Waller, "On testability of Differential Split-Level CMOS Circuits", IEEE Proc. -Circuits Devices Syst. , Vol. 141, No. 6, Dec 1994,pp. 191-194
- L. G Heller, Etal. ,"Cascode Voltage Switch Logic: A Differential CMOS Logic Family", Proceedings of 1984 IEEE International Solid-State Circuits Conference, pp. 16-17.
- Ila Gupta,Neha Arora,Dr. B. P. Singh,"Design and analysis of 2:1 multiplexer for high performance digital systems'', IJECT, Vol. 3, Issue 1, Jan-March 2012
- Daniel D. Gajski, "Principles of Digital Design'',Prentice Hall publishers,1997,pp. 178-182
- Weiqiang Zhang, LinfengLi,Jianping Hu,"Design Techniques of P-Type CMOS Circuits for Gate-Leakage Reduction in Deep Sub-micron ICs",IEEE International Midwest Symposium ,Circuits and Systems, 2009. MWSCAS '09,2-5Aug, 2009, pp. 551-554
- Dae Woon Kang,Yong-Bin Kim,"Design of enhanced differential cascode voltage switch logic(EDCVSL) circuits for high fan-in gate'',ASIC/SOC conference,2002,15th annual IEEE international,25-28sept 2002,pp. 309-3013.
- Nehru K. ,Shanmugam,A. , Darmilathenmozhi,G. ,"Design of low power ALU using 8T FA and PTL based MUX circuits'',Advances in Engineering,Science and Management(ICAESM),IEEE international conference,30-31 march 2012,pp. 724-730.
- M. Morris Mano,"Digital Logic design" ,Prentice Hall publishers, Aug 2001,pp. 116-120
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