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Analysis of 64- bit RC5 Encryption Algorithm for Pipelined Architecture

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International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 96 - Number 20
Year of Publication: 2014
Authors:
Ashmi Singh
Puran Gour
Braj Bihari Soni
10.5120/16912-7004

Ashmi Singh, Puran Gour and Braj Bihari Soni. Article: Analysis of 64- bit RC5 Encryption Algorithm for Pipelined Architecture. International Journal of Computer Applications 96(20):26-31, June 2014. Full text available. BibTeX

@article{key:article,
	author = {Ashmi Singh and Puran Gour and Braj Bihari Soni},
	title = {Article: Analysis of 64- bit RC5 Encryption Algorithm for Pipelined Architecture},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {96},
	number = {20},
	pages = {26-31},
	month = {June},
	note = {Full text available}
}

Abstract

In modern days data transmission through a channel requires more security. Security based more important transmission is comparatively better & believable than simple transmission. The aim of this work to use RC5 algorithm for encryption and decryption of data for secure data transmission from one place to another place for proper communication purposes. Today this is utmost importance to send information confidentially through network without any risk for hackers or unauthorized possibility to access from the network. This urgently require security implementation devices in network for well secured transmission of data. Symmetric encryption cores provide data protection through the use of secret key only known as encryption, whereas decryption deals with the yield at the end of communication path. Today world require secure transmission through cryptographic algorithm. Keeping view in mind the proposed well defined RC5 architecture have been taken, based on the fact for suitability of each operation for encryption, high speed processing and possibility of area reduction. The work results of the study clearly indicate that logic implementation by this hardware is maximum clock frequency of 179 MHz and areas reduced to 50% as compare with the results of design of previous worker. The propose design is described in verilog, synthesized by Xilinx synthesis technology.

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