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Efficient Comparator based Sum of Absolute Differences Architecture for Digital Image Processing Applications

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International Journal of Computer Applications
© 2014 by IJCA Journal
Volume 96 - Number 4
Year of Publication: 2014
Authors:
Narendra C. P
K. M. Ravi Kumar
10.5120/16781-6365

Narendra C P and Ravi K M Kumar. Article: Efficient Comparator based Sum of Absolute Differences Architecture for Digital Image Processing Applications. International Journal of Computer Applications 96(4):17-24, June 2014. Full text available. BibTeX

@article{key:article,
	author = {Narendra C. P and K. M. Ravi Kumar},
	title = {Article: Efficient Comparator based Sum of Absolute Differences Architecture for Digital Image Processing Applications},
	journal = {International Journal of Computer Applications},
	year = {2014},
	volume = {96},
	number = {4},
	pages = {17-24},
	month = {June},
	note = {Full text available}
}

Abstract

The prolific use of images & videos in portable devices, raised the need to develop the efficient architectures for the ever increasing demand of portability with low power and high performance quality metrics. However the images and videos are the information's to be stored, but there compression while storing is the important part. This paper introduces a basic hardware component "comparator" for the compression architectures. Comparator augments as general purpose core to Sum of Absolute difference (SAD) architecture used for the object recognition, generation of disparity maps of the stereo images and for estimating the motion in videos. The Subtraction part of the comparator is optimized by providing the parallel computation in processing the 2's complement operation. Transistor stacking and Logic optimization concepts are utilized to reduce the leakage power of the comparator design. 4-bit wide Comparator with "smallest of two binary numbers" functionality is modeled using Verilog HDL and synthesized using Synopsys Design Compiler. The design was mapped to 65nm technological library node and results were benchmarked with respect to standard ASIC design methodology. The proposed architectures have resulted in reduced leakage power about 7- 42 % for different proposed architectures and enabled the different corners for analysis.

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