Efficient Comparator based Sum of Absolute Differences Architecture for Digital Image Processing Applications

Abstract

The prolific use of images & videos in portable devices, raised the need to develop the efficient architectures for the ever increasing demand of portability with low power and high performance quality metrics. However the images and videos are the information's to be stored, but there compression while storing is the important part. This paper introduces a basic hardware component "comparator" for the compression architectures. Comparator augments as general purpose core to Sum of Absolute difference (SAD) architecture used for the object recognition, generation of disparity maps of the stereo images and for estimating the motion in videos. The Subtraction part of the comparator is optimized by providing the parallel computation in processing the 2's complement operation. Transistor stacking and Logic optimization concepts are utilized to reduce the leakage power of the comparator design. 4-bit wide Comparator with "smallest of two binary numbers" functionality is modeled using Verilog HDL and synthesized using Synopsys Design Compiler. The design was mapped to 65nm technological library node and results were benchmarked with respect to standard ASIC design methodology. The proposed architectures have resulted in reduced leakage power about 7- 42 % for different proposed architectures and enabled the different corners for analysis.

References

• Sumit K Chatterjee and Indrajit Chakrabarti, "A Fast and Low-power VLSI Architecture for Half-pixel Motion Estimation Using Two-step Search Algorithm for HDTV Application", IETE Journal of Research, VOL 57, Issue 3, May-Jun 2011.
• Stephan Wong, Stamatis Vassiliadis, and Sorin Cotofana "A Sum of Absolute Differences Implementation in FPGA Hardware", International Journal of Electrical and Computer Engineering 4:9 2009.
• C Hisham, K Komal, and Amit K Mishra, "Low power and less area architecture for integer motion estimation", International Journal of Electrical and Computer Engineering 4:9 2009.
• Joaquin Olivares, Ignacio Benavides and et. al. , "Minimum Sum of Absolute Differences implementation in a single FPGA device", Dept. of Electro-technics and Electronics, University of Cordoba, Spain.
• D. V. Manjunatha, G. Sainarayanan, "Power Efficient Sum of Absolute Difference Algorithms for video Compression", IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197 Volume 1, Issue 6 (Mar. – Apr. 2013), PP 10-18.
• Craig Watman & David Austin, et. al, "Fast Sum of Absolute Differences Visual Landmark Detector", Department of Systems Engineering, RSISE, Australian National University, Canberra, ACT 0200 Australia.
• Lin, Pao-Yen. "Basic Image Compression Algorithm and Introduction to JPEG Standard. " National Taiwan University, Taipei, Taiwan, ROC, 2009.
• Weste, Neil, and David Harris. "CMOS Vlsi Design. " A Circuits and Systems perspective, Pearson Addison Wesle, 2005.
• Manjunatha, D. V. , and G. Sainarayanan. "Low-Power Sum of Absolute Difference Architecture for Video Coding. " Emerging Research in Electronics, Computer Science and Technology. Springer India, 2014. 335-341.
• Yang, Shengqi, et al. "Accurate stacking effect macro-modeling of leakage power in sub-100 nm circuits. " 18th International Conference on VLSI Design. IEEE, 2005.
• Wiltgen, A. ; Escobar, K. A. ; Reis, A. I. ; Ribas, R. P. , "Power consumption analysis in static CMOS gates," Integrated Circuits and Systems Design (SBCCI), 2013 26th Symposium on, vol. , no. , pp. 1,6, 2-6 Sept. 2013.
• ChandraMohan U, "Low Power Area Efficient Digital Counters", Proceedings of the 7th VLSI Design and Test Workshops, VDAT, August 2003.
• Mentor Graphics Corporation, ModelSim SE Tutorial, 2008.
• Website, www. ee. bgu. ac. il, "Introduction to Digital VLSI"
• Website,"http://allofvlsi. blogspot. in/2010/01/synthesis-flow. html".

Index Terms

Keywords