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Reseach Article

Techniques for Sub-threshold Leakage Reduction in Low Power CMOS Circuit Designs

by Amrita Oza, Poonam Kadam
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 97 - Number 15
Year of Publication: 2014
Authors: Amrita Oza, Poonam Kadam
10.5120/17082-7533

Amrita Oza, Poonam Kadam . Techniques for Sub-threshold Leakage Reduction in Low Power CMOS Circuit Designs. International Journal of Computer Applications. 97, 15 ( July 2014), 10-13. DOI=10.5120/17082-7533

@article{ 10.5120/17082-7533,
author = { Amrita Oza, Poonam Kadam },
title = { Techniques for Sub-threshold Leakage Reduction in Low Power CMOS Circuit Designs },
journal = { International Journal of Computer Applications },
issue_date = { July 2014 },
volume = { 97 },
number = { 15 },
month = { July },
year = { 2014 },
issn = { 0975-8887 },
pages = { 10-13 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume97/number15/17082-7533/ },
doi = { 10.5120/17082-7533 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:24:10.858202+05:30
%A Amrita Oza
%A Poonam Kadam
%T Techniques for Sub-threshold Leakage Reduction in Low Power CMOS Circuit Designs
%J International Journal of Computer Applications
%@ 0975-8887
%V 97
%N 15
%P 10-13
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Power dissipation is a key consideration in the design of nano-scale CMOS VLSI circuits. Various techniques have been proposed for reduction of leakage in CMOS transistors. As the technology is emerging power dissipation due to leakage current has become a major contributor of total power consumption in the integrated devices. For high performance and device reliability, reduction of power consumption is highly desirable. Thus the importance of low power circuits has increased currently. The trend of scaling down has led to the increase in sub threshold leakage current and hence static power consumption. In this paper the different leakage reduction techniques for deep submicron technologies are focused comprehensively. The predominating sub threshold leakage current problem can be overcome by techniques like stacking of transistors, power gating, optimal body bias voltage generation at the circuit level thus providing a large range of choices for low-leakage power VLSI designers.

References
  1. P. Saini, R. Mishra "Leakage Power reduction in CMOS circuits," International Journal of Computer Applications, vol. 55, No. 8, October 2012.
  2. K. Kaur, A. Noor "Minimization of Leakage Current in VLSI Design," International Journal of Scientific and Engineering Reasearch, vol. 03, Issue 4, April 2012.
  3. S. Rao Ijjada, B. Ramparamesh, Dr. V. Malleshwara Rao "Reduction of Power Dissipation in Logic Circuits," International Journal of Computer Applications, vol. 24, No. 6, June 2011.
  4. Anjana R. , Dr. Ajay Kumar somukwar "Analysis of Sub threshold Leakage Reduction Techniques in Deep Sub Micron Regime for CMOS VLSI Circuits," Emerging Trends in VLSI, Embedded System, Nano Electronics and Telecommunication System (ICEVENT), 2013 International Conference on , vol. , no. , pp. 1,5, 7-9 Jan. 2013.
  5. Farzan Fallah, Massoud Pedram, "Standby and Active Leakage Current control and Minimisation in CMOS VLSI Circuits," unpublished.
  6. Mark C. Johnson, D. Somashekhar, K. Roy "Leakage control with efficient use of transistor stacks in single threshold CMOS," Very Large Scale Integration (VLSI) Systems, IEEE Trans. , vol. 10, no. 1, pp. 1,5, Feb. 2002.
  7. C. Jagadeesh, R. Nagendra, Neelima koppala "Design and Analysis of Different Types of Sleepy Methods for Future Technolodies," International Journal of Engineering Trends and Tecnology, vol. 4, Issue 4, April 2013.
  8. Body Effect and Body Biasing Copyright© 2011 SuVolta, Inc. Suvolta. com
  9. K. Roy, S. Mukhopadhyay, Mahmoodi-Meimand, H. , "Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits," Proc. of the IEEE , vol. 91, no. 2, pp. 305,327, February 2003.
  10. Kyung-Ki Kim; Yong-Bin Kim, "Optimal Body Biasing for Minimum Leakage Power in Standby Mode," Circuits and Systems, ISCAS 2007, IEEE International Symposium on , vol. , no. , pp. 1161, 27-30 May 2007.
  11. Heungjun Jeon, Yong-Bin Kim, Minsu Choi, "Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems," Instrumentation and Measurement, IEEE Trans. , vol. 59, no. 5, pp. 1127,1133, May 2010.
Index Terms

Computer Science
Information Sciences

Keywords

Sub threshold leakage low power stacking of transistors power-gating and body bias voltage.