Digital images are often corrupted by impulsive noise also called as salt and pepper noise [1]. It occurs in the form of sharp black or white pixels within the image. An efficient non-linear filter to reduce such noise is the median filter. The main advantage being the preserving of edges as compared to the mean filter. In larger images like satellite images the median filter algorithm needs larger time for processing. A vhdl implementation of such filter shows drastic reduction in processing time. An attempt is made to implement 3X3 median filter on FPGA, using pipeline design and implement the circuit using the concept of finite state machines.

Impulse noise Median filter finite state machine.