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Reseach Article

Performance Enhancement by Splitting ALU in Error Resilient Low Cost Processors

by Naveen Kumar, Rahul Raj Choudhary, Pradeep Dimri
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 97 - Number 19
Year of Publication: 2014
Authors: Naveen Kumar, Rahul Raj Choudhary, Pradeep Dimri
10.5120/17116-7750

Naveen Kumar, Rahul Raj Choudhary, Pradeep Dimri . Performance Enhancement by Splitting ALU in Error Resilient Low Cost Processors. International Journal of Computer Applications. 97, 19 ( July 2014), 24-28. DOI=10.5120/17116-7750

@article{ 10.5120/17116-7750,
author = { Naveen Kumar, Rahul Raj Choudhary, Pradeep Dimri },
title = { Performance Enhancement by Splitting ALU in Error Resilient Low Cost Processors },
journal = { International Journal of Computer Applications },
issue_date = { July 2014 },
volume = { 97 },
number = { 19 },
month = { July },
year = { 2014 },
issn = { 0975-8887 },
pages = { 24-28 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume97/number19/17116-7750/ },
doi = { 10.5120/17116-7750 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:24:33.620861+05:30
%A Naveen Kumar
%A Rahul Raj Choudhary
%A Pradeep Dimri
%T Performance Enhancement by Splitting ALU in Error Resilient Low Cost Processors
%J International Journal of Computer Applications
%@ 0975-8887
%V 97
%N 19
%P 24-28
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Performance enhancement has always been a primary design goal for designers. Modern automation technology demands for reliable low cost controllers, required for specific applications. The restricted resources limits the number of functional units available on a processor which results into lowered performance. The better performance can be achieved with splitting existing functional unit into smaller independent units. The split of arithmetic and logic unit into two independent units namely arithmetic unit and logic unit, provides the facility for simultaneous operation by both of the units. This results into lesser execution time. The simulator Simplescalar has been modified to simulate split ALU. The benchmarks are run in order to collect performance statistics. The simulation parameters, including execution time have been recorded for standard simulator having integral ALU unit, and for split ALU unit and further compared to show enhanced performance with split ALU.

References
  1. Viney Kumar, Rahul Raj, and Virendra Singh, 'FREP: A Soft-Error Resilient Pipelined RISC Architecture', IEEE East-West Design and Test Symposium (EWDTS) 2009, Moscow, Russia, Sep 2009, pp. 196-199.
  2. Eric Rotenberg, 'AR-SMT: A Microarchitectural Approach to Fault tolerance in Microprocessors', Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, 1999. Page(s):84 - 91.
  3. Wang N. J. and Patel S. J. , 'ReStore: Symptom Based Soft Error Detection in Microprocessors, IEEE Transactions on Architecture, Volume 3, Issue 3, July-Sept. 2006 Page(s): 188 - 201.
  4. C. Metra D. Rossi, M. Omana, A. Jas, and R. Galivanche, 'Function-Inherent Code Checking: A New Low Cost On-Line Testing Approach For High Performance Microprocessor Control Logic', 13th European Test Symposium, May 2008.
  5. Naseer, Riaz Bhatti, Rashed Zafar Draper, Jeff, 'Analysis of Soft Error Mitigation Techniques for Register Files in IBM Cu-08 90nm Technology',Circuits and Systems, 2006. MWSCAS'06.
  6. Qureshi, M. K. ; Mutlu, O. Patt, Y. N. , 'Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors', Dependable Systems and Networks, 2005. DSN 2005. Proceedings. International Conference, Volume , Issue , 28 June-1 July 2005 Page(s): 434 - 443
  7. G. Sohi, M. Franklin, and K. K. Saluja, 'A Study of Time-Redundant Fault Tolerance Techniques for High-Performance Pipelined Computers', Nineteenth International Symposium on Fault-Tolerant Computing, FTCS-19, Jun 1989 Page(s):436 -443.
  8. J. B. Nickel, and A. K. Somani, 'REESE: A Method of Soft Error Detection in Microprocessors', Proc. of Int. Conf. on Dependable Systems and Networks, 2001.
  9. S. Kim, A. K. Somani, 'SSD: an Affordable Fault Tolerant Architecture for Superscalar Processors', in Proc. of Int. Symp. on Dependable Computing, pp. 27-34, 2001.
  10. S. Shamshiri, H. Esmaeilzadeh, and Z. Navabi, 'Instruction-level test methodology for CPU core self-testing', ACM Trans. Des. Autom. Electron. Syst. , vol. 10, no. 4, pp. 673689, Oct. 2005.
  11. SimpleScalarR, SimpleScalar LLC toolset by Todd Austine, www. simplescalar. com
Index Terms

Computer Science
Information Sciences

Keywords

Reliable low cost controllers functional units split ALU simulation parameters.