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Reseach Article

An Efficient Multi-Path Delay Commutator Architecture

by G. Narmadha, S. Deivasigamani, K. Balasubadra
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 98 - Number 17
Year of Publication: 2014
Authors: G. Narmadha, S. Deivasigamani, K. Balasubadra
10.5120/17275-7704

G. Narmadha, S. Deivasigamani, K. Balasubadra . An Efficient Multi-Path Delay Commutator Architecture. International Journal of Computer Applications. 98, 17 ( July 2014), 21-23. DOI=10.5120/17275-7704

@article{ 10.5120/17275-7704,
author = { G. Narmadha, S. Deivasigamani, K. Balasubadra },
title = { An Efficient Multi-Path Delay Commutator Architecture },
journal = { International Journal of Computer Applications },
issue_date = { July 2014 },
volume = { 98 },
number = { 17 },
month = { July },
year = { 2014 },
issn = { 0975-8887 },
pages = { 21-23 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume98/number17/17275-7704/ },
doi = { 10.5120/17275-7704 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T22:26:55.706723+05:30
%A G. Narmadha
%A S. Deivasigamani
%A K. Balasubadra
%T An Efficient Multi-Path Delay Commutator Architecture
%J International Journal of Computer Applications
%@ 0975-8887
%V 98
%N 17
%P 21-23
%D 2014
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The Appearance of radix-22 was a milestone in the design of pipelined FFT hardware architectures. Later, radix-22 was extended to radix-2K. In the feed forward architectures radix-2K can be used for any number of parallel samples which is a power of two. Indeed, it is shown that feed forward structures are more efficient than feedback ones when several samples in parallel must be processed. As a results shown that the proposed designs are efficient both in area and perform ace, being possible to obtain throughputs of the order of GSamples/s as well as very low latencies.

References
  1. L. Yang, K. Zhang, H. Liu, J. Huang, and S. Huang, "An efficient locally pipelined FFT processor", IEEE Trans. Circuits Syst. II, Exp. Briefs, Vol. 53, no. 7, pp. 585-589, Jul. 2006.
  2. Y. W. Lin and C. Y. Lee, "Design of an FFT/IFFT processor for MIMO OFDM systems", IEEE Trans. Circuits Syst. I, Reg. papers, Vol. 54, no. 4, pp. 807-815, Apr. 2007.
  3. M. Ayinala, M. J. Brown, and Keshab K. Parhi, "Pipelined Parallel FFT Architectures via Folding Transformations", IEEE Trans. VLSI systems, Vol. 20, No. 6, June2012.
  4. Bevan M. Baas, "A low-power High-performance, 1024-point FFT Processor", IEEE journal of solid state circuits, Vol. 34, No. 3, March1999.
  5. M. Garrido, K. K. Parhi, and J. Grajal, "A pipelined FFT architecture for real-valued signals", IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 56 No. 12, 2634-2643, Dec. 2009.
  6. Y. N. Chang, "An efficient VLSI architecture for normal I/O order pipeline FFT design", IEEE Trans. Circuits Syst. II, Briefs, Vol. 555, No. 12, pp. 1234-1238, Dec. 2008.
  7. M. Garrido, O. Gustafsson, and J. Grajal, "Accurate rotations based on co-efficient scaling", IEEE Trans. Circuits Syst. II, Exp. Briefs, Vol. 58, N0. 10, pp. 662-666, Oct. 2011.
Index Terms

Computer Science
Information Sciences

Keywords

Fast Fourier Transform (FFT) Radix-2k Multipath Delay Commutator (MDC) Pipelined Architecture Very Large-Scale Integration (VLSI).