The week's pick
Reseach Article
A Combined Approach of IVC and GR for Leakage Power Reduction in CMOS VLSI Digital Circuit
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 98 - Number 5 |
| Year of Publication: 2014 |
| Authors: Uday Panwar, Kavita Khare |
10.5120/17181-7276
|
Uday Panwar, Kavita Khare . A Combined Approach of IVC and GR for Leakage Power Reduction in CMOS VLSI Digital Circuit. International Journal of Computer Applications. 98, 5 ( July 2014), 33-37. DOI=10.5120/17181-7276
Abstract
In Deep Sub-Micron (DSM) technology, leakage power dissipation consumes the substantial percentage of the total power dissipation and rises exponentially according to the International Technology Roadmap for Semiconductor (ITRS). Leakage power decreases battery life for the entire portable battery operated device such as mobile phones, laptop and cam coder etc. VLSI design constraints are always area, power and delay. To reduce the leakage power losses several techniques has been proposed that proficiently reduces leakage power dissipation Leakage power in CMOS VLSI circuits can be controlled at the circuit level. This paper has considered two run time leakage reduction mechanics i. e. Input Vector Control (IVC) and Gate Replacement (GR). When the first technique is applied on the CMOS circuit, 30% average leakage power reduction is achieved where as 46% of average leakage power is reduces due to GR technique. The Maximum leakage reduction is achieved of 41. 2% and 73% due to IVC and GR techniques respectively. These techniques have been applied on ISCAS benchmark circuit C17 using TSMC0. 18um technology file on HSPICE simulator.
References
- Abdoul Rjoub , " A fast input vector control approach for sub-threshold leakage power reduction", Almotasem Bellah Alajlouni, Hassan Almanasrah, 2012.
- J. Halter and F. Najm, "A Gate-Level Leakage Power Reduction Method for Ultra Low Power CMOS Circuits," Proc. Of ClCC, pp. 475-478, 1997.
- Behnaz Mortazavi, "Modeling leakage in sub-micron CMOS technologies" Azad University of Tehran-Iran, Jun. 1995.
- L. Wei, et. al, "Design and optimization of low voltage high performance dual threshold CMOS circuits," Proc. Of DAC, pp. 489-494, Jun. 1998.
- S. Mutoh, et. al, "I-V Power Supply High-speed Digital Circuit Technology with Multi-Threshold Voltage CMOS", IJSSC, vol. 30, no. 8, pp. 847-854, Aug. 1995.
- ] T. Kurado, et. al, "A 0. 9V, 150 MHz, 10-mW, 4mm2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold (Vt) Scheme," IEEE Journal of Solid Stare Circuits, vol. 3 1, no. 11, pp. 1770 - 1779, Nov. 1996.
- F. Assaderaghi,"DTMOS: Its Derivatives and variations, and their Potential Applications," Proc. of 12th Intnl. Conference on Microelectronics, pp. 9-19, 2000.
- D. Duarte, Y. Tsai, N. Vijaykrishnan and M. Irwin, "Evaluating Run-Time Techniques for Leakage Power Reduction," Proc. Of 15th Intnl. Conjerence on VLSI Design, pp. 31-38,2002
- A heuristic to search a low leakage vector for CMOS circuits", Rahul M. Rao, Frank Liu, Jeffrey L. Burns, Richard Brown, Austin research labs, 2006.
- Nikhil Jayakumar, " An algorithm to minimize leakage through simultaneous input vector control and circuit modification", Sunil P Khatri, Texas, 2007.
- F. Aloul, S. Hassoun, K. Sakallah, D. Blaauw, "Robust SAT-BasedSearch Algorithm for Leakage Power eduction," PATMOS, 2002.
- A. Abdollahi, F. Fallah, and M. Pedram, "Leakage current reduction in CMOS VLSI circuits by input vector control," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 12, no. 2, pp. 140–154, Feb. 2004.
- R. M. Rao, F. Liu, J. L. Burns, and R. B. Brown, "A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits", IEEE International Conference on Computer-Aided Design, November 2003.
- Yu wang,Xiaoming Chen,Wenping wang, Yu cao Yuan Xie and Huazhong Yang, "Leakage power and circuit aging Cooptimization by Gate replacement Techniques" ,IEEE transactions on very large scale system ,vol. 19 no. 4, April 2011
- D. Lee,W. Kwong, D. Blaauw, and D. Sylvester, "Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage", ACM/IEEE Design Automation Conference, pp. 175-180, June 2003.
- K. Chopra and S. B. K. Vrudhula, "Implicit Pseudo Boolean Enumeration Algorithms for Input Vector Control", ACM/IEEE Design Automation Conference, pp. 767-772, 2004
- K. Chopra and S. B. K. Vrudhula, "Implicit pseudo-Boolean enumeration algorithms for input vector control," in Proc. DAC, 2004, pp. 767–772.
- F. Gao and J. P. Hayes, "Exact and heuristic approaches to input vector control for leakage power reduction," in Proc. ICCAD, 2004, pp. 527–532.
- M. C. Johnson, D. Somasekhar, and K. Roy, "Models and algorithms for bounds on leakage in CMOS circuits," IEEE Trans. Comput. -Aided Des. Integr. Circuits Syst. , vol. 18, no. 6, Jun. 1999, pp. 714–725.
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