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Improved SNR and ENOB of Sigma-Delta Modulator for Post Simulation and High Level Modeling of Built-in-Self-Test Scheme

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IJCA Proceedings on National Conference Potential Research Avenues and Future Opportunities in Electrical and Instrumentation Engineering
© 2015 by IJCA Journal
ACEWRM 2015 - Number 3
Year of Publication: 2015
Authors:
Anil Kumar Sahu
Vivek Kumar Chandra
G. R. Sinha

Anil Kumar Sahu, Vivek Kumar Chandra and G.r.sinha. Article: Improved SNR and ENOB of Sigma-Delta Modulator for Post Simulation and High Level Modeling of Built-in-Self-Test Scheme. IJCA Proceedings on National Conference Potential Research Avenues and Future Opportunities in Electrical and Instrumentation Engineering ACEWRM 2015(3):11-14, May 2015. Full text available. BibTeX

@article{key:article,
	author = {Anil Kumar Sahu and Vivek Kumar Chandra and G.r.sinha},
	title = {Article: Improved SNR and ENOB of Sigma-Delta Modulator for Post Simulation and High Level Modeling of Built-in-Self-Test Scheme},
	journal = {IJCA Proceedings on National Conference Potential Research Avenues and Future Opportunities in Electrical and Instrumentation Engineering},
	year = {2015},
	volume = {ACEWRM 2015},
	number = {3},
	pages = {11-14},
	month = {May},
	note = {Full text available}
}

Abstract

This paper demonstrates a Graphical User Interface (GUI) of 2nd order Sigma-Delta modulator which is used to check the non-idealities of the circuit in BIST Scheme. High -level modeling of the parameters is done with the help of Matlab - Simulink and the parameters like Signal to Noise Ratio (SNR) & Effective Number of Bits (ENOB) are calculated. The value of SNR and ENOB are found to be 108 dB and 18 bits respectively Since the value of SNR and ENOB are increased it makes the respective signal power and Resolution better. The Graphical User Interface (GUI) of overall model has been successfully implemented after modeling of non-idealities for BIST technique not only avoids depending on the off-chip automatic test equipment (ATE) and reduces the test cost but increases the controllability and observability of the circuit under test also that improves the fault coverage .

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