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A Review on Architecture of High Speed data Communication for USB 2. 0 device using FPGA

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IJCA Proceedings on National Conference Potential Research Avenues and Future Opportunities in Electrical and Instrumentation Engineering
© 2015 by IJCA Journal
ACEWRM 2015 - Number 3
Year of Publication: 2015
Authors:
Zessha Mishra
Anil Kumar Sahu

Zessha Mishra and Anil Kumar Sahu. Article: A Review on Architecture of High Speed data Communication for USB 2.0 device using FPGA. IJCA Proceedings on National Conference Potential Research Avenues and Future Opportunities in Electrical and Instrumentation Engineering ACEWRM 2015(3):15-18, May 2015. Full text available. BibTeX

@article{key:article,
	author = {Zessha Mishra and Anil Kumar Sahu},
	title = {Article: A Review on Architecture of High Speed data Communication for USB 2.0 device using FPGA},
	journal = {IJCA Proceedings on National Conference Potential Research Avenues and Future Opportunities in Electrical and Instrumentation Engineering},
	year = {2015},
	volume = {ACEWRM 2015},
	number = {3},
	pages = {15-18},
	month = {May},
	note = {Full text available}
}

Abstract

In this paper a review on USB2. 0 using this innovative approach presented the authors own concept of USB receiver/transmitter architecture. The various concept was implemented in hardware description language to provide model for simulations. Simultaneously the code is synthesizable, and may be physically implemented in programmable logic devices. Selected details of construction and functionality of USB protocol were reported. Described The Universal Serial Bus (USB) Transceiver Macro cell Interface (UTMI) is a two wire, bi- directional serial bus interface between USB devices through D+ and D- lines. There are three functional blocks present in USB controller; those are Serial Interface Engine (SIE), UTMI and Device Specific Logic (DSL). When the data is received on the serial bus, it is decoded, bit unstuffed and is sent to receive shift register. Designed a High speed easy to use peripheral interfaces like USB 2. 0 . Implemented hardware on a Spartan-3 FPGA is easily capable of handling data throughputs as high as what USB 2. 0 demands. Using dedicated resources such as multipliers it is also possible to do signal processing tasks on these data.

References

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