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Modeling a Floating Gate EEPROM Device using Finite Element Analysis

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IJCA Proceedings on National Conference on Advancements in Alternate Energy Resources for Rural Applications
© 2015 by IJCA Journal
AERA 2015 - Number 2
Year of Publication: 2015
Authors:
Abhay Bindal
Abhijeet Kumar
Kamal Kant Sharma
Akhil Gupta

Abhay Bindal, Abhijeet Kumar, Kamal Kant Sharma and Akhil Gupta. Article: Modeling a Floating Gate EEPROM Device using Finite Element Analysis. IJCA Proceedings on National Conference on Advancements in Alternate Energy Resources for Rural Applications AERA 2015(2):1-3, December 2015. Full text available. BibTeX

@article{key:article,
	author = {Abhay Bindal and Abhijeet Kumar and Kamal Kant Sharma and Akhil Gupta},
	title = {Article: Modeling a Floating Gate EEPROM Device using Finite Element Analysis},
	journal = {IJCA Proceedings on National Conference on Advancements in Alternate Energy Resources for Rural Applications},
	year = {2015},
	volume = {AERA 2015},
	number = {2},
	pages = {1-3},
	month = {December},
	note = {Full text available}
}

Abstract

The present paper illustrates the modelling and simulation of an Electrically Erasable Programmable Read-Only-Memory (EEPROM) using COMSOL Multiphysics. The inbuilt stationary study computes the current voltage response of the device for both charged and uncharged cases of the floating gate. It is also illustrated herewith how time dependent studies on COMSOL Multiphysics are used to simulate the transient voltage pulses input at the control gate. It is also worth mentioning that EEPROM uses a FLOTOX (Floating Gate Tunnelling Oxide) device, which enables the pulses applied at the control gate to tunnel between the floating gate and the semiconductor material, thereby allowing storing or erasing a data. A write-erase cycle is performed, where the negative charges initially stored on the floating gate is subsequently removed by applying a high drain voltage and zero gate voltage. The model described here in the present paper is a single cell of an EEPROM, which has the capability to store only a single bit of data. As an extended version of this paper, many such cells can be connected together by using "enabling word lines" to simulate a large array of EEPROM. COMSOL Multiphysics provides us with a spice electrical circuit module which facilitates the connection of individual cells through nodes and terminals.

References

  • Chih-Ping Chung, Kuei-Shu Chang-Liao and Chun-Yuan Chen, "Enhanced performance of Single Poly-Silicon EEPROM cell with a Tungsten Finger Coupling Structure by Full CMOS," IEEE transactions on Electron devices, vol. 61, no. 9, pp. 3075-3080, sept. 2014.
  • Torricelli, F. ; Milani, L. ; Richelli, A. ; Colalongo, L. ; Pasotti, M. ; Kovacs-Vajna, Z. M. , " Half-MOS Single-Poly EEPROM Cell in Standard CMOS Process," IEEE Transactions on Electron Devices, vol. 60, no. 6, pp. 1892-1897, June 2013.
  • Nyukin A. , kravtsov A. , Timoshin S, Zubov I. , "A low cost EEPROM design for passive RFID tags," Fourth International Conference on Communications and Electronics (ICCE), pp. 443-446, Aug. 1-3, 2012.
  • Meir Janai, Boaz Eitan, Assaf Shappir, Eli Lusky, Ilan Bloom and Guy Cohen, "Data retention Reliability model of NROM Nonvolatile Memory Products," IEEE Transaction on Device and Materials Reliability, vol. 4, no. 3, pp. 404-415, sept. 2004.
  • Greg Atwood, "Future Directions and challenges for ETox Flash Memory Scaling," IEEE Transaction on Device and Materials Reliability, vol. 4, no. 3, pp. 301-305, Sept. 2004.
  • Roberto Bez, Emilio Camerlenghi, Alberto Modelli, and Angelo Visconti, "Introduction to Flash Memory," Proceedings of the IEEE, vol. 91, no. 4, pp. 489-502, April 2003.
  • F. Masuoka, M. Momodomi, Y. Iwata, and R. Shirota, "New ultra high density EPROM and Flash with NAND structure cell," in IEDM Tech. Dig. , 1987, pp. 552–555. 2001.
  • A. Modelli, A. Manstretta, and G. Torelli, "Basic feasibility constraints for multilevel CHE-programmed Flash memories," IEEE Trans. Electron Devices, vol. 48, pp. 2032–2042, Sept. 2001.
  • G. Campardo et al. , "40-mm 3-V-only 50-MHz 64-Mb 2-b/cell CHE NOR flash memory," IEEE J. Solid-State Circuits, vol. 35, pp. 1655–1667, Nov. 2000.
  • M. Lenzlinger and E. H. Snow, "Fowler-Nordheim Tunneling into Thermally Grown SiO2," J. Applied Physics, vol. 40, no. 1, pp. 278–283, 1969.
  • A. Concannon, S. Keeney, A. Mathewson, and C. Lombardi, "Two-Dimensional Numerical Analysis of Floating-Gate EEPROM Devices," IEEE Transactions on Electron Devices, vol. 40, no. 7, pp. 1258–1262, 1993.
  • A. P. Mathur, "Introdcution to microprocessors," Tata McGraw-Hill education, 1989, ISBN 0074602225, 9780074602225.