For the two level two type data cache model proposed in literature, the two cache levels are accessed for each reference to determine the cache is to be inclusive or exclusive. This is achieved by probing the index array of the cache levels. This paper proposes tag cache architecture for the two type data cache model. The tag array at level one is accessed to determine if a line is present in level one or level two by comparing the tag values. The cache levels are accessed based on the result of tag comparison. The tag array is enabled during the entire operation selectively enabling the cache lines in two levels. Energy consumption is reduced by this operation. A mathematical model for energy saving is developed and validated with SPEC2K benchmark with 99% energy saving.

1. Smith, A. J. 1982. Cache memories. ACM Computing Surveys (CSUR), 14(3), 473-530.
2. Agarwal, A. , Hennessy, J. , & Horowitz, M. 1989. An analytical cache model. ACM Transactions on Computer Systems (TOCS), 7(2), 184-215.
3. David. A. Patterson and John. L. Hennessy 2003 Computer Architecture: A Quantitative Approach, Morgan Kaufmann Publishers, 3rd edititon,
4. Li, L. , Kadayif, I. , Tsai, Y. F. , Vijaykrishnan, N. , Kandemir, M. , Irwin, M. J. , & Sivasubramaniam, A. 2002. Leakage energy management in cache hierarchies. In Parallel Architectures and Compilation Techniques, 2002. Proceedings. 2002 International Conference on (pp. 131-140). IEEE.
5. McFarling, S. 1992, April. Cache replacement with dynamic exclusion. InACM SIGARCH Computer Architecture News (Vol. 20, No. 2, pp. 191-200). ACM.
6. Powell, M. D. , Agarwal, A. , Vijaykumar, T. N. , Falsafi, B. , & Roy, K. 2001, December. Reducing set-associative cache energy via way-prediction and selective direct-mapping. In Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture (pp. 54-65). IEEE Computer Society.
7. Jouppi, N. P. , & Wilton, S. J. 1994, April. Tradeoffs in two-level on-chip caching. In Computer Architecture, 1994. , Proceedings the 21st Annual International Symposium on (pp. 34-45). IEEE.
8. Min, R. , Xu, Z. , Hu, Y. , & Jone, W. B. 2004. Partial tag comparison: A new technology for power-efficient set-associative cache designs. In VLSI Design, 2004. Proceedings. 17th International Conference on (pp. 183-188). IEEE.
9. Subha, S. 2009, June. A two-type data cache model. In Electro/Information Technology, 2009. eit'09. IEEE International Conference on (pp. 476-481). IEEE.
10. Subha S. 2011 December. An Energy Saving Tag Cache Model, IJCA, 36(8), pp. 38-43
11. Zhao, L. , Iyer, R. , Makineni, S. , Newell, D. , & Cheng, L. 2010, May. NCID: a non-inclusive cache, inclusive directory architecture for flexible and efficient cache hierarchies. In Proceedings of the 7th ACM international conference on Computing frontiers (pp. 121-130). ACM.
12. Zheng, Y. , Davis, B. T. , & Jordan, M. 2004. Performance evaluation of exclusive cache hierarchies. In Performance Analysis of Systems and Software, 2004 IEEE International Symposium on-ISPASS (pp. 89-96). IEEE.

Tag Cache Two-type Data Cache Energy Savings