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Study and Design of Low Power Universal Differential Current Conveyor

Published on December 2013 by Jyoti Singh, Ramkrishna Kundu, Dipayan Ghosh, Abhishek Pandey, Basab Bijoy Pal, Vijay Nath
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2nd International conference on Computing Communication and Sensor Network 2013
Foundation of Computer Science USA
CCSN2013 - Number 1
December 2013
Authors: Jyoti Singh, Ramkrishna Kundu, Dipayan Ghosh, Abhishek Pandey, Basab Bijoy Pal, Vijay Nath
93fdcd08-b755-4852-91fb-ed2b5057632a

Jyoti Singh, Ramkrishna Kundu, Dipayan Ghosh, Abhishek Pandey, Basab Bijoy Pal, Vijay Nath . Study and Design of Low Power Universal Differential Current Conveyor. 2nd International conference on Computing Communication and Sensor Network 2013. CCSN2013, 1 (December 2013), 35-38.

@article{
author = { Jyoti Singh, Ramkrishna Kundu, Dipayan Ghosh, Abhishek Pandey, Basab Bijoy Pal, Vijay Nath },
title = { Study and Design of Low Power Universal Differential Current Conveyor },
journal = { 2nd International conference on Computing Communication and Sensor Network 2013 },
issue_date = { December 2013 },
volume = { CCSN2013 },
number = { 1 },
month = { December },
year = { 2013 },
issn = 0975-8887,
pages = { 35-38 },
numpages = 4,
url = { /proceedings/ccsn2013/number1/14756-1310/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 2nd International conference on Computing Communication and Sensor Network 2013
%A Jyoti Singh
%A Ramkrishna Kundu
%A Dipayan Ghosh
%A Abhishek Pandey
%A Basab Bijoy Pal
%A Vijay Nath
%T Study and Design of Low Power Universal Differential Current Conveyor
%J 2nd International conference on Computing Communication and Sensor Network 2013
%@ 0975-8887
%V CCSN2013
%N 1
%P 35-38
%D 2013
%I International Journal of Computer Applications
Abstract

In this paper very low power CMOS universal differential difference current conveyor is designed. This is regarded as current mode circuits can be used for wireless communication. The gain, 3db bandwidth ,unity gain bandwidth, slew rate and phase margin at non inverting terminal was calculated as of 32. 33dB, 781MHz, 24 GHz, 934V/ms and 47 degree. The gain, 3db bandwidth ,unity gain bandwidth, slew rate and phase margin at inverting terminal was calculated as of 30dB, 756MHz, 15. 3 GHz, 934V/ms and 32. 4 degree . The circuit was simulated using Cadence analog and digital design tools. The used technology is gpdk 45nm.

References
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  12. Singh, J. Kundu, R. Ghosh, D. Pandey, A. Nath, V. " Design of low power universal differential difference current conveyor for wireless communication," 2nd International conference on Communication, Computing and Sensor Network vol. 4, pp. 8-10, Nov 2013
Index Terms

Computer Science
Information Sciences

Keywords

Operational Amplifiers (op-amps) Current Conveyor (ccii) Differential Difference Current Conveyor (ddcc) Complementary Metal Oxide Semiconductor Field Effect Transistor (cmos).