CFP last date
20 June 2024
Reseach Article

An Ultra Low Power Fast Locking CMOS Phase Locked Loop for Wireless Communication

Published on June 2015 by Suraj Kumar Saw, Sdk Verma, Bharat Gupta, Vijay Nath
International Conference on Computing, Communication and Sensor Network
Foundation of Computer Science USA
CCSN2014 - Number 1
June 2015
Authors: Suraj Kumar Saw, Sdk Verma, Bharat Gupta, Vijay Nath
547d282c-b2ab-41a5-a513-b6f4d352d108

Suraj Kumar Saw, Sdk Verma, Bharat Gupta, Vijay Nath . An Ultra Low Power Fast Locking CMOS Phase Locked Loop for Wireless Communication. International Conference on Computing, Communication and Sensor Network. CCSN2014, 1 (June 2015), 32-36.

@article{
author = { Suraj Kumar Saw, Sdk Verma, Bharat Gupta, Vijay Nath },
title = { An Ultra Low Power Fast Locking CMOS Phase Locked Loop for Wireless Communication },
journal = { International Conference on Computing, Communication and Sensor Network },
issue_date = { June 2015 },
volume = { CCSN2014 },
number = { 1 },
month = { June },
year = { 2015 },
issn = 0975-8887,
pages = { 32-36 },
numpages = 5,
url = { /proceedings/ccsn2014/number1/21421-5018/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Computing, Communication and Sensor Network
%A Suraj Kumar Saw
%A Sdk Verma
%A Bharat Gupta
%A Vijay Nath
%T An Ultra Low Power Fast Locking CMOS Phase Locked Loop for Wireless Communication
%J International Conference on Computing, Communication and Sensor Network
%@ 0975-8887
%V CCSN2014
%N 1
%P 32-36
%D 2015
%I International Journal of Computer Applications
Abstract

In this paper fast locking CMOS phase locked loop is proposed. It is designed using Cadence virtuoso gpdk 45nm CMOS technology. It is used 1 volt power supply for operation of the circuit. This proposed circuit will be very useful in clock generation in microprocessor, frequency synthesizer for cell phone, fast locking in digital aid circuits.

References
  1. B . Razvi, Design of ANALOG CMOS Integrated Circuits Tata Mc-Graw Hill (2003).
  2. Shao-Ku Kao, Fu-Jen Hsieh "A fast locking PLL with all-digital locked-aid circuit" International Journal of Electronics, 2013 Vol 100,No 2 p-245-258.
  3. Lin, C. -S. , Chien, T. -H. , Wey, C. -L. , Huang, C. -M. , and Juang, Y. -Z. (2009), 'An Edge Missing Compensator for Fast Settling Wide Locking Range Phase-locked Loop', IEEE Journal of Solid-state Circuits, 44, 3102–3110
  4. Park, K. , and Park, I. -C. (2009), 'Fast Frequency Acquisition Phase Frequency Detectors with Prediction-Based Edge Blocking', in Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 1891–1894 (2009)
  5. Liu, S. , and Shi, Y. (2008), 'Fast Locking and High Accurate Current Matching Phase-locked Loop', in Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, pp. 1136–1139.
  6. Chiu, W. -H. , Chan, T. -S. , and Lin, T. -H. (2007), 'A 5. 5-GHz 16-mW Fast-locking Frequency Synthesizer in 0. 18-mm CMOS', in Proceedings of the IEEE Asian Solid-state Circuits Conference, pp. 456–459
  7. Lincoln Lai Kan Leung and Howard C. Luong, "A 1-V 9. 7-mW CMOS Frequency synthesizer for IEEE 802. 11a Transceivers", IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 1, pp. 39-48, Jan. 2008.
  8. Kashyap K. Patel, Nilesh D. Patel "A Phase Frequency Detector and Charge Pump For DPLL Using 0. 18µm CMOS Technology" International Journal of Emerging Technology and Advanced Engineering Volume 3, Issue1, January 2013
Index Terms

Computer Science
Information Sciences

Keywords

Phase Locked Loop (pll) Phase Detector (pd) Charge Pump Voltage Controlled Oscillator (vco) Loop Filter Frequency Divider.