An Ultra Low Power Fast Locking CMOS Phase Locked Loop for Wireless Communication

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IJCA Proceedings on International Conference on Computing, Communication and Sensor Network
© 2015 by IJCA Journal
CCSN 2014 - Number 1
Year of Publication: 2015
Authors:
Suraj Kumar Saw
Sdk Verma
Bharat Gupta
Vijay Nath

Suraj Kumar Saw, Sdk Verma, Bharat Gupta and Vijay Nath. Article: An Ultra Low Power Fast Locking CMOS Phase Locked Loop for Wireless Communication. IJCA Proceedings on International Conference on Computing, Communication and Sensor Network CCSN 2014(1):32-36, June 2015. Full text available. BibTeX

@article{key:article,
	author = {Suraj Kumar Saw and Sdk Verma and Bharat Gupta and Vijay Nath},
	title = {Article: An Ultra Low Power Fast Locking CMOS Phase Locked Loop for Wireless Communication},
	journal = {IJCA Proceedings on International Conference on Computing, Communication and Sensor Network},
	year = {2015},
	volume = {CCSN 2014},
	number = {1},
	pages = {32-36},
	month = {June},
	note = {Full text available}
}

Abstract

In this paper fast locking CMOS phase locked loop is proposed. It is designed using Cadence virtuoso gpdk 45nm CMOS technology. It is used 1 volt power supply for operation of the circuit. This proposed circuit will be very useful in clock generation in microprocessor, frequency synthesizer for cell phone, fast locking in digital aid circuits.

References

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