The data loss is the measure performance parameter for evaluating the network topologies in NoC. In the source routing, route computation for packet transmission from source to destination is done before the transmission. In this paper we analysis the packet loss during the link down in mesh interconnection network topology with source routing using simulation.

1. Zhu Ding, "Adaptive Hybrid Switching Technique for Parallel Computing System", 2000
2. http://pages.cs.wisc.edu/~tvrdik/5/html/Section5.html
3. Dally W.J. and Towles B., "Principles and Practices of Interconnection Networks", Morgan Kaufmann Publishers an Imprint of Elsevier Inc. ISBN: 0-12-200751-4. 2004.
4. Axel Jantsch and Hannu Tenhunen, "Networks on Chip", Kluwer Academic Publishers. ISBN: 1-4020-7392-5. 2003.
5. J. Flich, P. lopez, M. P. Malumbers and J. Duato. "Improving the Performance of Regular Networks with Source Routin", Proceeding of the IEEE International Conference on Parallel Processing. 21-24 Aug. 2000. Page(s) 353-361.
6. Palesi M., Holsmark R., Kumar S. and Catania V., "Application Specific Routing Algorithms for Networks on Chip", IEEE Transactions on Parallel and Distributed Systems, Vol. 20, No. 3, March 2009.
7. Ge-Ming Chiu. "The Odd-Even Turn Model for Adaptive Routing" IEEE Transactions on Parallel and Distributed Systems, Vol. 11, No. 7, July 2000.
8. A. Patooghy, H. Sarbazi-Azad, "Performance comparison of partially adaptive routing algorithms. In 20th International Conference on Advanced Information Networking and Applications", 2006. AINA 2006. Volume 2, 18-20 April 2006.
9. Palesi M., Holsmark R., Kumar S. and Catania V., "A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems", In International Conference on Hardware-Software Codesign and System Synthesis, Seoul, Korea, October 22-25, 2006.
10. M.E. Gomez, P. Lopez, J.Duato, "A Memory-Effective routing Strategy for regular Interconnection Networks", in Proc. Int. Parallel and Distributed Prossing Symp., 2005.
11. Y-R. Sun, S. Kumar, and A. Jantsch, "Simulation and evaluation of a network-on-chip architecture using NS-2," Proceedings of the IEEE NorChip Conference, 2002.
12. S. Kumar et al., "A network-on-chip architecture and design methodology," Proceedings of the International Symposium on VLSI (ISVLSI), 2002, pp. 117-124.
13. A. Hegedus, G. M. Maggio,, and L. Kocarev, "A NS-2 simulator utilizing chaotic maps for network-on-chip traffic analysis," Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), vol. 4, 2005, pp. 3375-3378.
14. L. Bononi and N. Concer, "Simulation and analysis of network-on-chip architectures: Ring, Spidergon, and 2D Mesh," Proceedings of Design, Automation and Test in Europe (DATE) Conference and Exhibition (Designers' Forum), 2006, pp. 154-159.
15. J. Xu, W. Wolf, J. Henkel, and S. Chakradhar, "A design methodology for application-specific networks-onchip," ACM Transactions on Embedded Computing Systems, vol. 5, May 2006, pp. 263-280.
16. M. Moadeli, A. Shahrabi, W. Vanderbauwhede, and M. Ould-Khaoua, "An analytical performance model for the Spidergon NoC," Proceedings of the 21st International Conference on Advanced Information Networking and Applications, 2007, pp. 1014-1021.
17. S. Suboh, M. Bakhouya, S. Lopez-Buedo, and T. El- Ghazawi., "Simulation-based approach for evaluating on-chip interconnect architectures", SPL Proc., pages 75–80, 2008

Interconnection Networks Mesh Source Routing Noc.