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Low Power Dynamic Logic Circuit with Leakage Reduction Technique

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IJCA Proceedings on International Conference on Emergent Trends in Computing and Communication
© 2015 by IJCA Journal
ETCC 2015 - Number 1
Year of Publication: 2015
Authors:
Swati Sucharita Guru
Nirmal Kumar Rout

Swati Sucharita Guru and Nirmal Kumar Rout. Article: Low Power Dynamic Logic Circuit with Leakage Reduction Technique. IJCA Proceedings on International Conference on Emergent Trends in Computing and Communication ETCC 2015(1):18-21, September 2015. Full text available. BibTeX

@article{key:article,
	author = {Swati Sucharita Guru and Nirmal Kumar Rout},
	title = {Article: Low Power Dynamic Logic Circuit with Leakage Reduction Technique},
	journal = {IJCA Proceedings on International Conference on Emergent Trends in Computing and Communication},
	year = {2015},
	volume = {ETCC 2015},
	number = {1},
	pages = {18-21},
	month = {September},
	note = {Full text available}
}

Abstract

In this paper a technique is proposed to reduce the leakage power of domino logic. In this proposed circuit pseudo dynamic buffer is used to reduce the power dissipation due to the precharge pulse propagation and leakage control transistor is used to reduce the leakage power. The leakage control transistors increase the resistance of the path from supply voltage to ground. As a result the leakage current is reduced. The cadence spectre tool at 180nm technology is used for simulation. The proposed logic is compared with the existing logic design. It is observed from the simulation that the power delay product and leakage current is reduced up to 32% and 10% respectively as compared to pseudo dynamic buffer based domino logic.

References

  • Anders M. , Mathew S. , Bloechel B. , Thompson S. , Krishnamurthy R. , Soumyanath K. , Borkar S. , IEEE ISSCC (2002), pp. 410-411. A 6. 5 GHz 130 nm single-ended dynamic ALU and instruction-scheduler loop,
  • Xu-guang Sun, Zhi-gang Mao, Feng-chang Lai, Proceedings of the IEEE ASia-Pacific Conference on ASIC, 2002, pp. 205-208. A 64 bit parallel CMOS adder for high performance processors,
  • Neil H. E. Weste, David Harris, 2004. Principles of CMOS VLSI Design: A System Perspective,(3rd ed. )Addison-Wesley
  • Mendoza-Hernandez F. , M. Linares-Aranda, V. Champac, Proceedings of the lEE Circuits, Devices and Systems, vol. 153 (2006), pp. 565-573 No. 6, Dec,Noisetolerance improvement in dynamic CMOS logic circuits
  • Ji-Ren Y. , Karlsson I. , Svensson C. , A true single-phase-clock dynamic CMOS circuit technique, lEEE Journal of Solid-State Circuits, 22 (Oct. ) (1987), pp. 899-90 I.
  • Fang Tang, Amine Bermark,Zhouye Gu," INTEGRATION",the vlsijournal 45(2012) 395-404. Low power dynamic logic design using a pseudo dynamic buffer,
  • Kursun V. , Friedman G. E. , Domino logic with variable threshold voltage keeper, IEEE Transactions on VLSI Systems, 11 (6) (2003), pp. 1080-1093.
  • Rabey Jan M. , Chandrakasan Anantha, Nikolic Borivoje, Prentice Hall (2003). Digital Integrated Circuits- A Design Perspective.
  • Hanchate Narender, Ranganathan Nagarajan ,LECTOR: A technique for leakage reduction in CMOS circuit, IEEE transactions on very large scale integration (VLSI) systems, vol. 12, no. 2, february 2004.
  • Narendra S. , Borkar S, De V. , Antoniadis V. and Chandrakasan A. P. ,Scaling of Stack Effect and Its Applica- tion for Leakage Reduction, IEEE International Sympo- sium on Low Power Electronics and Design, August 2001, pp. 195-200.