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Reseach Article

Low Power Dynamic Logic Circuit with Leakage Reduction Technique

Published on September 2015 by Swati Sucharita Guru, Nirmal Kumar Rout
International Conference on Emergent Trends in Computing and Communication
Foundation of Computer Science USA
ETCC2015 - Number 1
September 2015
Authors: Swati Sucharita Guru, Nirmal Kumar Rout
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Swati Sucharita Guru, Nirmal Kumar Rout . Low Power Dynamic Logic Circuit with Leakage Reduction Technique. International Conference on Emergent Trends in Computing and Communication. ETCC2015, 1 (September 2015), 18-21.

@article{
author = { Swati Sucharita Guru, Nirmal Kumar Rout },
title = { Low Power Dynamic Logic Circuit with Leakage Reduction Technique },
journal = { International Conference on Emergent Trends in Computing and Communication },
issue_date = { September 2015 },
volume = { ETCC2015 },
number = { 1 },
month = { September },
year = { 2015 },
issn = 0975-8887,
pages = { 18-21 },
numpages = 4,
url = { /proceedings/etcc2015/number1/22331-4552/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Emergent Trends in Computing and Communication
%A Swati Sucharita Guru
%A Nirmal Kumar Rout
%T Low Power Dynamic Logic Circuit with Leakage Reduction Technique
%J International Conference on Emergent Trends in Computing and Communication
%@ 0975-8887
%V ETCC2015
%N 1
%P 18-21
%D 2015
%I International Journal of Computer Applications
Abstract

In this paper a technique is proposed to reduce the leakage power of domino logic. In this proposed circuit pseudo dynamic buffer is used to reduce the power dissipation due to the precharge pulse propagation and leakage control transistor is used to reduce the leakage power. The leakage control transistors increase the resistance of the path from supply voltage to ground. As a result the leakage current is reduced. The cadence spectre tool at 180nm technology is used for simulation. The proposed logic is compared with the existing logic design. It is observed from the simulation that the power delay product and leakage current is reduced up to 32% and 10% respectively as compared to pseudo dynamic buffer based domino logic.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Low Power Domino Logic Leakage Current Cad Tool