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Analytical Drain Current Model for Symmetrical Gate Underlap DGMOSFET
| International Conference on Communication, Circuits and Systems 2012 |
| Foundation of Computer Science USA |
| IC3S - Number 3 |
| June 2013 |
| Authors: Sudhansu Kumar Pati, Hemant Pardeshi, Godwin Raj, Chandan Kumar Sarkar, Arghyadeep Sarkar, N Mohan Kumar |
| b19e1e8a-5f99-4e3a-b660-501b66a8fd1b |
Sudhansu Kumar Pati, Hemant Pardeshi, Godwin Raj, Chandan Kumar Sarkar, Arghyadeep Sarkar, N Mohan Kumar . Analytical Drain Current Model for Symmetrical Gate Underlap DGMOSFET. International Conference on Communication, Circuits and Systems 2012. IC3S, 3 (June 2013), 26-28.
Abstract
The drain current model of symmetrical Underlap DGMOSFET is evaluated for subthreshold region. Model data is verified with simulation data for validation of the proposed model. For validation the drain current is evaluated with respect to gate to source potential. The drain current is calculated with variation of gate length, underlap length and silicon body thickness. As the gate length and underlap length increases, the drain current decreases and as silicon body thickness increases, increase of drain current is observed.
References
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