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Reseach Article

Performance Analysis of AlInN/GaN Underlap DG MOSFET for varying Underlap and Gate length

Published on June 2013 by Hemant Pardeshi, N. Mohankumar, Chandan Kumar Sarkar
International Conference on Communication, Circuits and Systems 2012
Foundation of Computer Science USA
IC3S - Number 4
June 2013
Authors: Hemant Pardeshi, N. Mohankumar, Chandan Kumar Sarkar
7dbe669b-f857-4db1-b489-64416b302d18

Hemant Pardeshi, N. Mohankumar, Chandan Kumar Sarkar . Performance Analysis of AlInN/GaN Underlap DG MOSFET for varying Underlap and Gate length. International Conference on Communication, Circuits and Systems 2012. IC3S, 4 (June 2013), 1-3.

@article{
author = { Hemant Pardeshi, N. Mohankumar, Chandan Kumar Sarkar },
title = { Performance Analysis of AlInN/GaN Underlap DG MOSFET for varying Underlap and Gate length },
journal = { International Conference on Communication, Circuits and Systems 2012 },
issue_date = { June 2013 },
volume = { IC3S },
number = { 4 },
month = { June },
year = { 2013 },
issn = 0975-8887,
pages = { 1-3 },
numpages = 3,
url = { /proceedings/ic3s/number4/12302-1340/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Communication, Circuits and Systems 2012
%A Hemant Pardeshi
%A N. Mohankumar
%A Chandan Kumar Sarkar
%T Performance Analysis of AlInN/GaN Underlap DG MOSFET for varying Underlap and Gate length
%J International Conference on Communication, Circuits and Systems 2012
%@ 0975-8887
%V IC3S
%N 4
%P 1-3
%D 2013
%I International Journal of Computer Applications
Abstract

In this work, we investigate the performance of 18nm gate length AlInN/GaN Heterostructure Underlap Double Gate MOSFETs, using 2D Sentaurus TCAD simulation. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of major device performance metrics such as DIBL, SS, delay, and Ion/Ioff ratio have been done for varying gate length (Lg) and underlap length (Lun). Impressive results for Delay, Ion, and DIBL are obtained. The results indicate that there is a need to optimize the Ioff and SS values for specific logic design.

References
  1. M. Alomari et al. , "InAlN/GaN MOSHEMT With Self-Aligned Thermally Generated Oxide Recess," IEEE Electron Device Letters, vol. 30, no. 11, 2009, pp. 1131-1133.
  2. A. Dadgar, F. Schulze, and A. Diez, "High-sheet-charge – carrier-density AlInN ? GaN field-effect transistors on Si (111)," Applied Physics Letters, vol. 85, no. 22, 2004, pp. 5400-5402.
  3. V. Adivarahan, J. Yang, A. Koudymov, G. Simin, and M. A. Khan, "Stable CW Operation of Field-Plated GaN-AlGaN MOSHFETs at 19 W/mm," IEEE Electron Device Letters, vol. 26, no. 8, 2005, pp. 535-537.
  4. C. Liu, et al. , "Enhanced device performance of AlGaN/GaN HEMTs using HfO2 high-k dielectric for surface passivation and gate oxide," Semiconductor Science and Technology, vol. 22, 2007, pp. 522-527.
  5. M. Marso et al. , "Origin of Improved RF Performance of AlGaN/GaN MOSHFETs Compared to HFETs," IEEE Transactions on Electron Devices, vol. 53, no. 7, 2006, pp. 1517-1523.
  6. M. A. Khan, X. Hu, et al. , "AlGaN/GaN metal – oxide – semiconductor heterostructure field-effect transistors on SiC substrates," Applied Physics Letters, vol. 77, 2000, pp. 1339-1341.
  7. V. Adivarahan et al. , "Submicron Gate SiN3/AlGaN /GaN - Metal-Insulator-Semiconductor Heterostructure Field Effect Transistor," IEEE Electron Device Letters, vol. 24, no. 9, 2003, pp. 541-543.
  8. G. Ji, H. -G. Liu, et al. , "Physical modeling based on hydrodynamic simulation for the design of InGaAs/InP double heterojunction bipolar transistors ," Chinese Physics B, vol. 21, no. 5, 2012, pp. 058501-1 - 058501-1.
Index Terms

Computer Science
Information Sciences

Keywords

Underlap Heterostructure 2deg Hemt Ultra Thin Body (utb) Dibl Ss Interface Traps