This paper focuses on reducing the Write Power consumption and delay of a SRAM cell in 32 nm technology. Static Random Access Memory (SRAM) is an important memory device for storing data on a chip. In CMOS, whatever chips and memory devices we see today, are actually made up of the layouts of metals and poly-Si on a highly pure silicon wafer. As the need for fast circuits has grown so, has the power consumption. In SRAM cells write operation is the most power consuming one. With the help of the new proposed design of 7-T SRAM write power can be reduced by about 7. 7%, and write delay by 5%; apart from reducing the area of the chip being used by a single SRAM cell by 20. 5%. The design has been implemented and simulated using Microwind 3. 1 and Dsch 3. 5 software.

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Cmos Low Power Delay Sram