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Improvising Low Power SRAM Cell in 32 nm Technology with the use of an Extra nMOST

Published on June 2013 by Saurabh, Anamika Anand, Anjali Sinha
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International Conference on Communication, Circuits and Systems 2012
Foundation of Computer Science USA
IC3S - Number 4
June 2013
Authors: Saurabh, Anamika Anand, Anjali Sinha
bdf53de0-2447-4307-abab-af4e7591fddc

Saurabh, Anamika Anand, Anjali Sinha . Improvising Low Power SRAM Cell in 32 nm Technology with the use of an Extra nMOST. International Conference on Communication, Circuits and Systems 2012. IC3S, 4 (June 2013), 4-6.

@article{
author = { Saurabh, Anamika Anand, Anjali Sinha },
title = { Improvising Low Power SRAM Cell in 32 nm Technology with the use of an Extra nMOST },
journal = { International Conference on Communication, Circuits and Systems 2012 },
issue_date = { June 2013 },
volume = { IC3S },
number = { 4 },
month = { June },
year = { 2013 },
issn = 0975-8887,
pages = { 4-6 },
numpages = 3,
url = { /proceedings/ic3s/number4/12303-1343/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Communication, Circuits and Systems 2012
%A Saurabh
%A Anamika Anand
%A Anjali Sinha
%T Improvising Low Power SRAM Cell in 32 nm Technology with the use of an Extra nMOST
%J International Conference on Communication, Circuits and Systems 2012
%@ 0975-8887
%V IC3S
%N 4
%P 4-6
%D 2013
%I International Journal of Computer Applications
Abstract

This paper focuses on reducing the Write Power consumption and delay of a SRAM cell in 32 nm technology. Static Random Access Memory (SRAM) is an important memory device for storing data on a chip. In CMOS, whatever chips and memory devices we see today, are actually made up of the layouts of metals and poly-Si on a highly pure silicon wafer. As the need for fast circuits has grown so, has the power consumption. In SRAM cells write operation is the most power consuming one. With the help of the new proposed design of 7-T SRAM write power can be reduced by about 7. 7%, and write delay by 5%; apart from reducing the area of the chip being used by a single SRAM cell by 20. 5%. The design has been implemented and simulated using Microwind 3. 1 and Dsch 3. 5 software.

References
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  3. E. Grosser, M. Stucchi, K. Maex and W. Dehaene "Read stability and write-ability analysis of SRAM cells for nanometer Technologies", IEEE Journal Of Solid-State Circuits, Vol. 41, NO. 11, November 2006.
  4. K. Itoh, M. Horiguchi, and H. Tanaka "Ultra-Low Voltage Nano-Scale Memories", Springer 2007.
  5. M. C. Wang, "Low Power Dual Word Line 6-Transistor SRAMs",WCECS 2009, Vol. 1, October 20-22, 2009.
  6. C. M. R. Prabhu and A. K. Singh " A proposed SRAM cell for low power consumption during write operation " Microelectronics International, 2009. Volume: 26.
Index Terms

Computer Science
Information Sciences

Keywords

Cmos Low Power Delay Sram