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Reseach Article

Design of Ultra Low Power LC VCO in 45 nm Standard CMOS Process

Published on June 2013 by Anindita Sahu, Sushanta K. Mandal
International Conference on Communication, Circuits and Systems 2012
Foundation of Computer Science USA
IC3S - Number 4
June 2013
Authors: Anindita Sahu, Sushanta K. Mandal
3d492c41-9727-46a0-8ee8-497a9f4aa9af

Anindita Sahu, Sushanta K. Mandal . Design of Ultra Low Power LC VCO in 45 nm Standard CMOS Process. International Conference on Communication, Circuits and Systems 2012. IC3S, 4 (June 2013), 17-20.

@article{
author = { Anindita Sahu, Sushanta K. Mandal },
title = { Design of Ultra Low Power LC VCO in 45 nm Standard CMOS Process },
journal = { International Conference on Communication, Circuits and Systems 2012 },
issue_date = { June 2013 },
volume = { IC3S },
number = { 4 },
month = { June },
year = { 2013 },
issn = 0975-8887,
pages = { 17-20 },
numpages = 4,
url = { /proceedings/ic3s/number4/12307-1349/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Communication, Circuits and Systems 2012
%A Anindita Sahu
%A Sushanta K. Mandal
%T Design of Ultra Low Power LC VCO in 45 nm Standard CMOS Process
%J International Conference on Communication, Circuits and Systems 2012
%@ 0975-8887
%V IC3S
%N 4
%P 17-20
%D 2013
%I International Journal of Computer Applications
Abstract

This work presents design of a fully integrated Voltage Control Oscillator (VCO) implemented in 45 nm standard CMOS process. The designed LC VCO operates at 9. 06 GHz with 634. 28µW power consumption from 1 V supply. The design achieves phase noise as -97. 48dBc/Hz at an offset of 1MHz and the figure of merit (FOM) of the LC-VCO is calculated as -178. 60dBc/Hz for the un-buffered VCO. For buffered VCO the phase noise becomes -97. 69dBc/Hz at an offset of 1MHz and the FOM is -178. 81dBc/Hz.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Rf Ic Lc Vco Cmos Process Low Power