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Reseach Article

Frequency Compensation of Two Stage Op-Amp using Triode Mode Compensation Stage

Published on June 2013 by Yogesh Yadav, Vijaya Bhadauria
International Conference on Communication, Circuits and Systems 2012
Foundation of Computer Science USA
IC3S - Number 5
June 2013
Authors: Yogesh Yadav, Vijaya Bhadauria
277ed1af-1ca4-49fe-8a68-75058dd15639

Yogesh Yadav, Vijaya Bhadauria . Frequency Compensation of Two Stage Op-Amp using Triode Mode Compensation Stage. International Conference on Communication, Circuits and Systems 2012. IC3S, 5 (June 2013), 16-18.

@article{
author = { Yogesh Yadav, Vijaya Bhadauria },
title = { Frequency Compensation of Two Stage Op-Amp using Triode Mode Compensation Stage },
journal = { International Conference on Communication, Circuits and Systems 2012 },
issue_date = { June 2013 },
volume = { IC3S },
number = { 5 },
month = { June },
year = { 2013 },
issn = 0975-8887,
pages = { 16-18 },
numpages = 3,
url = { /proceedings/ic3s/number5/12312-1362/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Communication, Circuits and Systems 2012
%A Yogesh Yadav
%A Vijaya Bhadauria
%T Frequency Compensation of Two Stage Op-Amp using Triode Mode Compensation Stage
%J International Conference on Communication, Circuits and Systems 2012
%@ 0975-8887
%V IC3S
%N 5
%P 16-18
%D 2013
%I International Journal of Computer Applications
Abstract

A frequency compensation technique for the improvement of unity gain bandwidth (UGB) and power supply rejection ratio (PSRR) of two stage operational amplifiers is presented in this paper. Performance of proposed op-amp is compared with classical miller compensated op-amp and op-amp proposed by G. Blakiewicz [13]. The technique exploits the triode mode operation of a MOSFET in the compensation stage which leads to the improvement in the UGB and Power Supply Rejection Ratio (PSRR). Small signal analysis for these parameters is carried out and theoretical improvements are verified through simulations in cadence VIRTUSO environment using UMC 0. 18 µm CMOS process technology.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Miller Compensation Triode Mode Mosfet Unity Gain Bandwidth Power Supply Rejection Ratio Phase Margin Op-amp