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Reseach Article

Power Aware Testing by Proper Don�t Care Filling of Test Patterns

Published on July 2013 by Oindrila Chakraborty, Parna Chakraborty, Priyanka Choudhury, Sambhu Nath Pradhan
International Conference on Communication, Circuits and Systems 2012
Foundation of Computer Science USA
IC3S - Number 6
July 2013
Authors: Oindrila Chakraborty, Parna Chakraborty, Priyanka Choudhury, Sambhu Nath Pradhan
8356f350-ae61-4672-973f-f0623ba49750

Oindrila Chakraborty, Parna Chakraborty, Priyanka Choudhury, Sambhu Nath Pradhan . Power Aware Testing by Proper Don�t Care Filling of Test Patterns. International Conference on Communication, Circuits and Systems 2012. IC3S, 6 (July 2013), 8-11.

@article{
author = { Oindrila Chakraborty, Parna Chakraborty, Priyanka Choudhury, Sambhu Nath Pradhan },
title = { Power Aware Testing by Proper Don�t Care Filling of Test Patterns },
journal = { International Conference on Communication, Circuits and Systems 2012 },
issue_date = { July 2013 },
volume = { IC3S },
number = { 6 },
month = { July },
year = { 2013 },
issn = 0975-8887,
pages = { 8-11 },
numpages = 4,
url = { /proceedings/ic3s/number6/12699-1335/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Communication, Circuits and Systems 2012
%A Oindrila Chakraborty
%A Parna Chakraborty
%A Priyanka Choudhury
%A Sambhu Nath Pradhan
%T Power Aware Testing by Proper Don�t Care Filling of Test Patterns
%J International Conference on Communication, Circuits and Systems 2012
%@ 0975-8887
%V IC3S
%N 6
%P 8-11
%D 2013
%I International Journal of Computer Applications
Abstract

With the advancement in automation, the importance of periodic testing of electronic circuits during their lifetime is increasing day by day. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Thus it is necessary to reduce the power consumption during test mode. This power is proportional to the number of node switching due to the feeding of successive test patterns. Test patterns generated by ATALANTA with –D option, contains don't cares. Efficient filling of don't cares in the patterns may reduce the number of switching when they are applied in succession. In this paper we have presented an approach based on Genetic Algorithm (GA) for don't care filling of the test patterns generated by Atalanta to reduce switching during circuit testing without compromising fault coverage. The proposed GA based formulation can save upto 58% power compared to existing approach. A trade-off between fault coverage and transitions also has been presented in this paper.

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Index Terms

Computer Science
Information Sciences

Keywords

Testing Low Power Genetic Algorithm Don't Care Fault Coverage Switching