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Reseach Article

Analysis and Implementation of a Full Adder Circuit using Xilinx Software

Published on August 2015 by Girdhari Agarwal, Bobbinpreet Kaur, Amandeep Kaur
International Conference on Advancements in Engineering and Technology
Foundation of Computer Science USA
ICAET2015 - Number 2
August 2015
Authors: Girdhari Agarwal, Bobbinpreet Kaur, Amandeep Kaur
2cf87a34-48d1-4eac-b461-2e4cafee9447

Girdhari Agarwal, Bobbinpreet Kaur, Amandeep Kaur . Analysis and Implementation of a Full Adder Circuit using Xilinx Software. International Conference on Advancements in Engineering and Technology. ICAET2015, 2 (August 2015), 5-8.

@article{
author = { Girdhari Agarwal, Bobbinpreet Kaur, Amandeep Kaur },
title = { Analysis and Implementation of a Full Adder Circuit using Xilinx Software },
journal = { International Conference on Advancements in Engineering and Technology },
issue_date = { August 2015 },
volume = { ICAET2015 },
number = { 2 },
month = { August },
year = { 2015 },
issn = 0975-8887,
pages = { 5-8 },
numpages = 4,
url = { /proceedings/icaet2015/number2/22211-4013/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Advancements in Engineering and Technology
%A Girdhari Agarwal
%A Bobbinpreet Kaur
%A Amandeep Kaur
%T Analysis and Implementation of a Full Adder Circuit using Xilinx Software
%J International Conference on Advancements in Engineering and Technology
%@ 0975-8887
%V ICAET2015
%N 2
%P 5-8
%D 2015
%I International Journal of Computer Applications
Abstract

This paper presents the novel method to analyze and implement a full adder circuit using VHDL Technology. The results include successful compilation of the VHDL code in the Xilinx software along with the waveforms that prove the legality of the truth table. This paper also shows the effective use of Xilinx software in the analysis of the full adder circuit. It shows the Register Transfer Level (RTL) schematic diagrams and technology schematic diagrams of the different VHDL architectural styles of modeling that include dataflow modeling, behavioral modeling and structural modeling. The analysis includes the detailed analysis of the fitter report and the timing report along with the synthesis report of the design summary. It also shows the chip floor plan of the full adder circuit.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Full Adder Xilinx Vhdl Design.