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Reseach Article

Implementation of 8-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC)

Published on July 2018 by Nancy Garg, Deepika Setia
International Conference on Advances in Emerging Technology
Foundation of Computer Science USA
ICAET2017 - Number 3
July 2018
Authors: Nancy Garg, Deepika Setia
90c5ee55-e075-4e4e-b8c1-4b009d99aea1

Nancy Garg, Deepika Setia . Implementation of 8-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). International Conference on Advances in Emerging Technology. ICAET2017, 3 (July 2018), 17-21.

@article{
author = { Nancy Garg, Deepika Setia },
title = { Implementation of 8-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) },
journal = { International Conference on Advances in Emerging Technology },
issue_date = { July 2018 },
volume = { ICAET2017 },
number = { 3 },
month = { July },
year = { 2018 },
issn = 0975-8887,
pages = { 17-21 },
numpages = 5,
url = { /proceedings/icaet2017/number3/29654-7073/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Advances in Emerging Technology
%A Nancy Garg
%A Deepika Setia
%T Implementation of 8-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC)
%J International Conference on Advances in Emerging Technology
%@ 0975-8887
%V ICAET2017
%N 3
%P 17-21
%D 2018
%I International Journal of Computer Applications
Abstract

A SAR ADC is presented in this paper with low power consumption. In this paper an asynchronous SAR logic is used which will reduce its power consumption as MSB bit evaluation and each bit evaluation time is different, due to which it provide high resolution for same power consumption. A dynamic comparator is used. It doesn't consume any static power which will reduce its power consumption. Vcm- based switching technique reduces its power as it maintains the common mode voltage. In this paper different block of a SAR ADC with their schematics and wave-forms is presented. This work is done by using Synopsys Galaxy Custom Designer Tool using 90nm CMOS technology in which power consumption by DAC is 33uW, Comparator consumes 43uW, SAR Logic consumes 55uW with frequency range 100MHz.

References
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  2. Walt Kester. ADC architectures II: Successive Approximation ADCs. MT-021 tutorial. Analog Devices. 2008.
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  5. Shreedevi Subramanya, Praveen J, Raghavendra Rao, "Analysis and Design of a New Modified Double-Tail Comparator For High Speed ADC Applications, international journal of innovative research in electrical, electronics, instrumentation and control engineering, Vol. 3, Special Issue 1, April 2015.
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  8. Jin-Yi Lin and Chih-Cheng Hsieh, "A 0. 3 V 10-bit 1. 17 f SAR ADC with merge andsplit switching in 90 nm cmos, ieee transactions on circuits and systems—i: regular papers, vol. 62, no. 1, January 2015.
  9. Yan-Jiun Chen, Kwuang-Han Chang, and Chih-Cheng Hsieh, "A 2. 02–5. 16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS, IEEE journal of solid-state circuits, vol. 51, no. 2, February 2016.
  10. Shuo-Wei Mike Chen, Robert W. Brodersen. A 6b 600MS/s 5. 3mW asynchronous ADC in 0. 13?m CMOS. IEEE international solid-state circuits conference, 1-4244-0079-1, 2006.
Index Terms

Computer Science
Information Sciences

Keywords

Sar Lower And Upper Dac Sample And Hold Circuit Bootstrapped Switch