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Compact Modeling of Tunnel Field Effect Transistor for Ultra-Low Power Design Applications

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IJCA Proceedings on International Conference on Advances in Emerging Technology
© 2018 by IJCA Journal
ICAET 2017 - Number 5
Year of Publication: 2018
Authors:
Ch. Pavan Kumar
K. Sivani

Ch. Pavan Kumar and K Sivani. Article: Compact Modeling of Tunnel Field Effect Transistor for Ultra-Low Power Design Applications. IJCA Proceedings on International Conference on Advancements in Engineering and Technology ICAET 2017(5):1-5, July 2018. Full text available. BibTeX

@article{key:article,
	author = {Ch. Pavan Kumar and K. Sivani},
	title = {Article: Compact Modeling of Tunnel Field Effect Transistor for Ultra-Low Power Design Applications},
	journal = {IJCA Proceedings on International Conference on Advancements in Engineering and Technology},
	year = {2018},
	volume = {ICAET 2017},
	number = {5},
	pages = {1-5},
	month = {July},
	note = {Full text available}
}

Abstract

The IC technology always aims at increasing the package density and the speed. The VLSI technology which is governed by MOSFETs for the past couple of decades. In an attempt to increase the package density the size of the MOSFETS has been scaled down. As the size of the MOSFETs is scaled downwards, sub-threshold leakage current and leakage power in the ICs is increasing. The continued scaling has reached stagnation and further miniaturization of the MOSFET is facing major challenges. The conventional MOSFETs at short channel lengths suffer from high OFF-state leakage currents. They also suffer from numerous other short channel effects. Hence, as an alternative to the MOSFETs, TFETs have been widely studied. TFETs have the asymmetrical source/drain doping profile and they operate as reverse-biased, gated p-i-n tunnel diodes. The on-off switching mechanism in TFETs can be achieved by the gate-voltage induced band-to-band tunneling (BTBT) at the source-channel tunnel junction only. Where as in conventional MOSFETs, only the carriers with energy exceeding the source-channel thermal barrier will contribute the on-state current. TFETs are promising candidates for low power CMOS applications. Modelling the effects of non-idealities on the drain current of a TFET is also an important aspect. High on-state current (Ion), high on-off ratio and steep SS are the critical aspects in TFET design. In, this paper the silvaco TCAD simulation results for both conventional MOSFET & SOI Tunnel field effect transistor and its structure are shown.

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