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Compact Modeling of Tunnel Field Effect Transistor for Ultra-Low Power Design Applications

Published on July 2018 by Ch. Pavan Kumar, K. Sivani
International Conference on Advances in Emerging Technology
Foundation of Computer Science USA
ICAET2017 - Number 5
July 2018
Authors: Ch. Pavan Kumar, K. Sivani
018767cd-46e2-4968-8b92-6f122b1eb7c5

Ch. Pavan Kumar, K. Sivani . Compact Modeling of Tunnel Field Effect Transistor for Ultra-Low Power Design Applications. International Conference on Advances in Emerging Technology. ICAET2017, 5 (July 2018), 1-5.

@article{
author = { Ch. Pavan Kumar, K. Sivani },
title = { Compact Modeling of Tunnel Field Effect Transistor for Ultra-Low Power Design Applications },
journal = { International Conference on Advances in Emerging Technology },
issue_date = { July 2018 },
volume = { ICAET2017 },
number = { 5 },
month = { July },
year = { 2018 },
issn = 0975-8887,
pages = { 1-5 },
numpages = 5,
url = { /proceedings/icaet2017/number5/29664-7109/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Advances in Emerging Technology
%A Ch. Pavan Kumar
%A K. Sivani
%T Compact Modeling of Tunnel Field Effect Transistor for Ultra-Low Power Design Applications
%J International Conference on Advances in Emerging Technology
%@ 0975-8887
%V ICAET2017
%N 5
%P 1-5
%D 2018
%I International Journal of Computer Applications
Abstract

The IC technology always aims at increasing the package density and the speed. The VLSI technology which is governed by MOSFETs for the past couple of decades. In an attempt to increase the package density the size of the MOSFETS has been scaled down. As the size of the MOSFETs is scaled downwards, sub-threshold leakage current and leakage power in the ICs is increasing. The continued scaling has reached stagnation and further miniaturization of the MOSFET is facing major challenges. The conventional MOSFETs at short channel lengths suffer from high OFF-state leakage currents. They also suffer from numerous other short channel effects. Hence, as an alternative to the MOSFETs, TFETs have been widely studied. TFETs have the asymmetrical source/drain doping profile and they operate as reverse-biased, gated p-i-n tunnel diodes. The on-off switching mechanism in TFETs can be achieved by the gate-voltage induced band-to-band tunneling (BTBT) at the source-channel tunnel junction only. Where as in conventional MOSFETs, only the carriers with energy exceeding the source-channel thermal barrier will contribute the on-state current. TFETs are promising candidates for low power CMOS applications. Modelling the effects of non-idealities on the drain current of a TFET is also an important aspect. High on-state current (Ion), high on-off ratio and steep SS are the critical aspects in TFET design. In, this paper the silvaco TCAD simulation results for both conventional MOSFET & SOI Tunnel field effect transistor and its structure are shown.

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Index Terms

Computer Science
Information Sciences

Keywords

Band-to-band Tunnelling Inversion Mode Subthreshold Swing Ultra-low Power Design