CFP last date
22 April 2024
Reseach Article

A Review Paper on Comparison of Multipliers based on Performance Parameters

Published on February 2015 by Savita Nair, Ajit Saraf
International Conference on Advances in Science and Technology
Foundation of Computer Science USA
ICAST2014 - Number 3
February 2015
Authors: Savita Nair, Ajit Saraf
5ca39755-eabb-433a-b4c0-686568672823

Savita Nair, Ajit Saraf . A Review Paper on Comparison of Multipliers based on Performance Parameters. International Conference on Advances in Science and Technology. ICAST2014, 3 (February 2015), 6-9.

@article{
author = { Savita Nair, Ajit Saraf },
title = { A Review Paper on Comparison of Multipliers based on Performance Parameters },
journal = { International Conference on Advances in Science and Technology },
issue_date = { February 2015 },
volume = { ICAST2014 },
number = { 3 },
month = { February },
year = { 2015 },
issn = 0975-8887,
pages = { 6-9 },
numpages = 4,
url = { /proceedings/icast2014/number3/19483-5031/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Advances in Science and Technology
%A Savita Nair
%A Ajit Saraf
%T A Review Paper on Comparison of Multipliers based on Performance Parameters
%J International Conference on Advances in Science and Technology
%@ 0975-8887
%V ICAST2014
%N 3
%P 6-9
%D 2015
%I International Journal of Computer Applications
Abstract

Among all the arithmetic operations that exist, a processor consumes most of its time and hardware resources in carrying out multiplication when compared to other operations like addition and subtraction. In this paper comparative study is done of four multipliers namely, Array multiplier, Modified booth multiplier, Wallace tree multiplier and modified Booth-Wallace tree multiplier based of various performance parameters like speed, area, power consumed and circuit complexity. It is always necessary to design a fast multiplier in VLSI so as to enhance system performance.

References
  1. Prasanna Raj P, Rao, Ravi, "VLSI Design and Analysis of Multipliers for Low Power", Intelligent Information Hiding and Multimedia Signal Processing, Fifth International Conference, pp. : 1354-1357, Sept. 2009
  2. "A Novel Parallel Multiply and Accumulate (V-MAC) Architecture Based On Ancient Indian Vedic Mathematics" Himanshu Thapliyal and Hamid Rarbania.
  3. "Low power and high speed 8x8 bit Multiplier Using Non- clocked Pass Transistor Logic" C. Senthilpari, Ajay Kumar Singh and K. Diwadkar, 1-4244-1355-9/07, 2007, IEEE.
  4. Kiat-seng Yeo and Kaushik Roy "Low-voltage, low power VLSI sub system" Mc Graw-Hill Publication.
  5. Jong Duk Lee, Yong Jin Yoony, Kyong Hwa Leez and Byung-Gook Park "Application of Dynamic Pass Transistor Logic to 8-Bit Multiplier" Journal of the Korean Physical Society, Vol. 38, No. 3, pp. 220-223, March 2001
  6. Rajendra Katti, "A Modified Booth Algorithm for High Radix Fixed point Multiplication", Very Large Scale Integration (VLSI) Systems, IEEE Transactions, vol. 2, pp. : 522-524, Dec. 1994.
  7. Jan M Rabaey, "Digital Integrated Circuits, A Design Perspective", Prentice Hall, Dec. 1995
  8. Aparna P R, Nisha Thomas, "Design and Implementation of High Performance Multiplier using HDL", 2011.
  9. "ASIC Implementation of 4 Bit Multipliers" Pravinkumar Parate, IEEE Computer society. ICETET, 2008. 25.
  10. Morris Mano, "Computer System Architecture", PP. 346- 347, 3rd edition, PHI. 1993.
  11. Jorn Stohmann Erich Barke, "A Universal Pezaris Array Multiplier Generator for SRAM-Based FPGAs" IMS- Institute of Microelectronics System, University of Hanover Callinstr, 34, D- 30167 Hanover, Germany.
  12. Moises E. Robinson and Ear Swartzlander, Jr. "A Reduction Scheme to Optimize the Wallace Multiplier" Department of Electrical and Computer Engineering, University of Texas at Austin, USA.
  13. Tam Anh Chu, "Booth Multiplier with Low Power High Performance Input Circuitary", US Patent, 6. 393. 454 B1, May 21, 2002.
  14. Sumit R. Vaidya and D. R. Dandekar, "Performance Comparison of Multipliers for Power-Speed Trade-off in VLSI Design", Recent advances in networking, VLSI and Signal Processing, ISSN: 1790-5117.
Index Terms

Computer Science
Information Sciences

Keywords

Array Multiplier Modified Booth Multiplier Modified Booth-wallace Tree Multiplier Wallace Tree Multiplier