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High Performance DCT Implementation using NEDA on FPGA

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IJCA Proceedings on International Conference in Computational Intelligence (ICCIA2012)
© 2012 by IJCA Journal
iccia - Number 1
Year of Publication: 2012
Authors:
Monika Zope
P. S. Mahajani

Monika Zope and P S Mahajani. Article: High Performance DCT Implementation using NEDA on FPGA. IJCA Proceedings on International Conference in Computational Intelligence (ICCIA2012) iccia(1):-, March 2012. Full text available. BibTeX

@article{key:article,
	author = {Monika Zope and P. S. Mahajani},
	title = {Article: High Performance DCT Implementation using NEDA on FPGA},
	journal = {IJCA Proceedings on International Conference in Computational Intelligence (ICCIA2012)},
	year = {2012},
	volume = {iccia},
	number = {1},
	pages = {-},
	month = {March},
	note = {Full text available}
}

Abstract

DCT is at the core of the most current generation of image and video compression standards including JPEG, H.261, H.263+, MPEG-1, 2, 4. Distributed arithmetic approach increases the speed and accuracy while reducing cost metrics, power and area of the DSP applications. As reducing cost is attracting more and more attention in application-specific integrated circuit design, there is an increasing demand for more efficient DA paradigms which can eliminate the need of using ROMs. At the same time, it is capable of meeting throughput constraints. To meet this demand New Distributed Arithmetic (NEDA) approach is introduced. NEDA features implementation without the need of multipliers as in conventional MAC approach, and at the same time, without the need of ROM as in DA approach. NEDA can also expose redundancy existing in the adder array consisting of entries of 0 and 1. VHDL code for calculation of DCT is written and this code is synthesized and simulated. The simulation results are verified by comparing with MATLAB results.

References

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