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FPGA Implementation of Viterbi Decoder

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IJCA Proceedings on International Conference in Computational Intelligence (ICCIA2012)
© 2012 by IJCA Journal
iccia - Number 1
Year of Publication: 2012
Authors:
Anubhuti Khare
Manish Saxena
Jagdish Patel

Anubhuti Khare, Manish Saxena and Jaagdish Patel. Article: FPGA Implementation of Viterbi Decoder. IJCA Proceedings on International Conference in Computational Intelligence (ICCIA2012) iccia(1):-, March 2012. Full text available. BibTeX

@article{key:article,
	author = {Anubhuti Khare and Manish Saxena and Jaagdish Patel},
	title = {Article: FPGA Implementation of Viterbi Decoder},
	journal = {IJCA Proceedings on International Conference in Computational Intelligence (ICCIA2012)},
	year = {2012},
	volume = {iccia},
	number = {1},
	pages = {-},
	month = {March},
	note = {Full text available}
}

Abstract

The main goal of this paper was resource-optimized implementation of the decoder on the target platform. It is well known that data transmissions over wireless channels are affected by attenuation, distortion, interference and noise, which affect the receiver’s ability to receive correct information. Convolutional encoding with Viterbi decoding is a powerful method for forward error correction. It has been widely deployed in many wireless communication systems to improve the limited capacity of the communication channels. In this paper, we present a Spartan XC3S400A field-programmable gate array implementation of Viterbi Decoder with a constraint length of 3 and a code rate of 1/3. The Viterbi Decoder is compatible with many common standards, such as DVB, 3GPP2, 3GPP LTE, IEEE 802.16, Hiperlan, and Intelsat IESS-308/309.

References

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