The use of Very Large Scale Integration (VLSI) technologies in high performance computing, wireless communication and consumer electronics has been growing at a very fast rate. Every generation of VLSI technology reduces feature size of transistor and leads to more powerful and compact wireless devices. The challenge of the advanced VLSI technology is the increase in the leakage power consumption. In deep sub– micron technology, standby leakage power dissipation has emerged as major design considerations. Leakage control is very important, especially for low power applications and handheld devices such as cellular phones and PDAs. In this paper two techniques such as transistor stacking and sleepy transmission gate for reducing leakage power are proposed. In these techniques, the resistance of the path from Vdd to ground is increased, so that significant reduction in static power is achieved with small increase in delay. This work analyses the leakage power and delay of three basic digital circuits inverter, NAND and NOR gates and the same can extended to any complex digital implementation. The circuits are simulated with MOSFET models of level 54 in 90 nm, 45nm and 32nm process technology.

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Leakage Power Static Power Sleep Transistor Threshold Voltage Stacking. Process Technology