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Implementation of High Speed Digital Multipliers using N-MOS based 1-Bit Full Adder

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IJCA Proceedings on International Conference on Emerging Trends in Informatics and Communication
© 2016 by IJCA Journal
ICETIC 2016 - Number 1
Year of Publication: 2016
Authors:
Shilpa Shaw
Chameli Mitra
Debanjana Datta

Shilpa Shaw, Chameli Mitra and Debanjana Datta. Article: Implementation of High Speed Digital Multipliers using N-MOS based 1-Bit Full Adder. IJCA Proceedings on International Conference on Emerging Trends in Informatics and Communication ICETIC 2016(1):33-37, September 2016. Full text available. BibTeX

@article{key:article,
	author = {Shilpa Shaw and Chameli Mitra and Debanjana Datta},
	title = {Article: Implementation of High Speed Digital Multipliers using N-MOS based 1-Bit Full Adder},
	journal = {IJCA Proceedings on International Conference on Emerging Trends in Informatics and Communication},
	year = {2016},
	volume = {ICETIC 2016},
	number = {1},
	pages = {33-37},
	month = {September},
	note = {Full text available}
}

Abstract

A processor devotes a considerable amount of processing time in performing arithmetic operations. Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than other arithmetic operations. So, Multiplier is one of the most important arithmetic units in processors and also a major source of power dissipation. Reducing the power dissipation, limiting the processing time and transistor count of multipliers are the key factors for designing various digital circuits and systems. To achieve high execution speed, parallel array multipliers are widely used. But these multipliers consume more power. The fundamental units to design a multiplier are adders. Additions are required to be performed using low- power, area-efficient circuits operating at greater speed. This paper aims at analyzing the power dissipation, circuit delay and finally PDP(Power-Delay Product) of parallel array multipliers by using only low power N-MOS based 1-bit full adder. The design has been done using DSCH 2. 6c and simulated using 0. 18um CMOS technology at 2. 5V supply with MICROWIND 2. 6a. Comparison of the results of post layout analysis with similar previous multiplier circuits proves efficiency of the proposed multiplier.

References

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