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Reseach Article

Implementation of High Speed Digital Multipliers using N-MOS based 1-Bit Full Adder

Published on September 2016 by Shilpa Shaw, Chameli Mitra, Debanjana Datta
International Conference on Emerging Trends in Informatics and Communication
Foundation of Computer Science USA
ICETIC2016 - Number 1
September 2016
Authors: Shilpa Shaw, Chameli Mitra, Debanjana Datta
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Shilpa Shaw, Chameli Mitra, Debanjana Datta . Implementation of High Speed Digital Multipliers using N-MOS based 1-Bit Full Adder. International Conference on Emerging Trends in Informatics and Communication. ICETIC2016, 1 (September 2016), 33-37.

@article{
author = { Shilpa Shaw, Chameli Mitra, Debanjana Datta },
title = { Implementation of High Speed Digital Multipliers using N-MOS based 1-Bit Full Adder },
journal = { International Conference on Emerging Trends in Informatics and Communication },
issue_date = { September 2016 },
volume = { ICETIC2016 },
number = { 1 },
month = { September },
year = { 2016 },
issn = 0975-8887,
pages = { 33-37 },
numpages = 5,
url = { /proceedings/icetic2016/number1/25873-4012/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Emerging Trends in Informatics and Communication
%A Shilpa Shaw
%A Chameli Mitra
%A Debanjana Datta
%T Implementation of High Speed Digital Multipliers using N-MOS based 1-Bit Full Adder
%J International Conference on Emerging Trends in Informatics and Communication
%@ 0975-8887
%V ICETIC2016
%N 1
%P 33-37
%D 2016
%I International Journal of Computer Applications
Abstract

A processor devotes a considerable amount of processing time in performing arithmetic operations. Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than other arithmetic operations. So, Multiplier is one of the most important arithmetic units in processors and also a major source of power dissipation. Reducing the power dissipation, limiting the processing time and transistor count of multipliers are the key factors for designing various digital circuits and systems. To achieve high execution speed, parallel array multipliers are widely used. But these multipliers consume more power. The fundamental units to design a multiplier are adders. Additions are required to be performed using low- power, area-efficient circuits operating at greater speed. This paper aims at analyzing the power dissipation, circuit delay and finally PDP(Power-Delay Product) of parallel array multipliers by using only low power N-MOS based 1-bit full adder. The design has been done using DSCH 2. 6c and simulated using 0. 18um CMOS technology at 2. 5V supply with MICROWIND 2. 6a. Comparison of the results of post layout analysis with similar previous multiplier circuits proves efficiency of the proposed multiplier.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Pdp c-mos N-mos Delay Power Multiplier Adder