High speed multiplication is one of the critical function in a range of very large scale integration (VLSI) applications. Multipliers find their importance in performing operations such as convolution, filtering and correlation in digital signal processing systems, microprocessors and graphic engines. Multiplication is an expensive and slow operation. Designing multipliers that are of low power, regular in layout and with high-speed are of substantial research interest. The speed of the multiplier can be improved by reducing the generated partial products. Of the many attempts that have been made to reduce the number of partial products generated in a multiplication process, one of the notable one is the Wallace tree multiplier. Wallace Tree CSA structures have been used to sum the partial products in reduced time. The existing Wallace tree architecture has considerable speed but due to various limitations faced, there arises the need for further improvement. In this project, the proposed system is a modified Wallace tree multiplier. In this paper Wallace tree multiplication is investigated and evaluated. Speed of traditional Wallace tree multiplier can be improved by using compressor techniques. Here the Wallace tree is constructed by conventional method with the help of compressors such as 3:2 compressor. Therefore, minimizing the number of adders used in a multiplier reduction will reduce the delay, thereby improving the speed of multiplication.

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Compressor Full Adder partial Product wallace Tree