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Analysis of GAA Tunnel FET using MATLAB

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IJCA Proceedings on International Conference on Emerging Trends in Technology and Applied Sciences
© 2015 by IJCA Journal
ICETTAS 2015 - Number 1
Year of Publication: 2015
Authors:
Praveen C S
Ajith Ravindran
Arathy Varghese

Praveen C S, Ajith Ravindran and Arathy Varghese. Article: Analysis of GAA Tunnel FET using MATLAB. IJCA Proceedings on International Conference on Emerging Trends in Technology and Applied Sciences ICETTAS 2015(1):30-35, September 2015. Full text available. BibTeX

@article{key:article,
	author = {Praveen C S and Ajith Ravindran and Arathy Varghese},
	title = {Article: Analysis of GAA Tunnel FET using MATLAB},
	journal = {IJCA Proceedings on International Conference on Emerging Trends in Technology and Applied Sciences},
	year = {2015},
	volume = {ICETTAS 2015},
	number = {1},
	pages = {30-35},
	month = {September},
	note = {Full text available}
}

Abstract

In order to improve the energy efficiency of next generation digital systems, transistors with Subthreshold Slope < 45 mV/decade of drain current are needed. Tunnel Field Effect Transistor (TFET) s are attractive new devices for low power applications by its virtues of reduced short channel effects, low off current and their potential for a small subthreshold swing. TFETs ON current (ION) is usually very low. One solution is a double gate instead of a single gate structure, which will provide ION improvement. A gate all around (GAA) structure is preferred for further ION improvement without sacrificing OFF current (IOFF). In order to obtain high ION and low IOFF, a GAA TFET is modeled with a virtue of meeting the low power and high performance specifications of International Technology Roadmap of Semiconductors (ITRS) projected to year 2020, at a reduced drain voltage(VDD) = 0. 5 V.

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