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Reseach Article

Analysis of GAA Tunnel FET using MATLAB

Published on September 2015 by Praveen C S, Ajith Ravindran, Arathy Varghese
International Conference on Emerging Trends in Technology and Applied Sciences
Foundation of Computer Science USA
ICETTAS2015 - Number 1
September 2015
Authors: Praveen C S, Ajith Ravindran, Arathy Varghese
7305d062-d44c-4f54-b1c8-4b96abc55eae

Praveen C S, Ajith Ravindran, Arathy Varghese . Analysis of GAA Tunnel FET using MATLAB. International Conference on Emerging Trends in Technology and Applied Sciences. ICETTAS2015, 1 (September 2015), 30-35.

@article{
author = { Praveen C S, Ajith Ravindran, Arathy Varghese },
title = { Analysis of GAA Tunnel FET using MATLAB },
journal = { International Conference on Emerging Trends in Technology and Applied Sciences },
issue_date = { September 2015 },
volume = { ICETTAS2015 },
number = { 1 },
month = { September },
year = { 2015 },
issn = 0975-8887,
pages = { 30-35 },
numpages = 6,
url = { /proceedings/icettas2015/number1/22376-2570/ },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Proceeding Article
%1 International Conference on Emerging Trends in Technology and Applied Sciences
%A Praveen C S
%A Ajith Ravindran
%A Arathy Varghese
%T Analysis of GAA Tunnel FET using MATLAB
%J International Conference on Emerging Trends in Technology and Applied Sciences
%@ 0975-8887
%V ICETTAS2015
%N 1
%P 30-35
%D 2015
%I International Journal of Computer Applications
Abstract

In order to improve the energy efficiency of next generation digital systems, transistors with Subthreshold Slope < 45 mV/decade of drain current are needed. Tunnel Field Effect Transistor (TFET) s are attractive new devices for low power applications by its virtues of reduced short channel effects, low off current and their potential for a small subthreshold swing. TFETs ON current (ION) is usually very low. One solution is a double gate instead of a single gate structure, which will provide ION improvement. A gate all around (GAA) structure is preferred for further ION improvement without sacrificing OFF current (IOFF). In order to obtain high ION and low IOFF, a GAA TFET is modeled with a virtue of meeting the low power and high performance specifications of International Technology Roadmap of Semiconductors (ITRS) projected to year 2020, at a reduced drain voltage(VDD) = 0. 5 V.

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Index Terms

Computer Science
Information Sciences

Keywords

Band To Band Tunneling Double Gate Tfet Gate All Around Structure Steep Subthreshold Slope